A new paradigm for synthesis and propagation of clock gating conditions

Proceedings - Design Automation Conference

Volumn , Issue , 2008, Pages 658-663

  Fraer, Ranan ^a   Kamhi, Gila ^a   Mhameed, Muhammad K ^a  

^a INTEL CORPORATION   (Israel)

Author keywords

Clock gating; Low power design

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER NETWORKS; DIGITAL INTEGRATED CIRCUITS; ENERGY CONSERVATION; INDUSTRIAL ENGINEERING;

CLOCK GATING; LOW-POWER DESIGN;

CLOCKS;

EID: 51549090036     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2008.4555900     Document Type: Conference Paper

References (7)

1. L. Benini and G. De Micheli. Automatic synthesis of low-power gated-clock finite-state machines, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 15(6), Jun. 1996
2. V. Tiwari, S. Malik and P. Ashar. Guarded evaluation: Pushing power management to logic synthesis/design. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 17(10), Oct. 1998.
3. L Benini, G De Micheli, E Macii, M Poncino and R. Scarsi. Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers. ACM Trans. on Design Automation of Electronic Systems, 4(4), 1999
4. W. Qing, M. Pedram and W. Xunwei. Clock-gating and its application to low power design of sequential circuits. IEEE Trans. on Circuits and Systems I: Fundamental Theory and Applications, 47 (3), Mar. 2000
5. P. Babighian, L. Benini and E. Macii. A scalable algorithm for RTL insertion of gated clocks based on ODCs computation. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 24(1), Jan. 2005.
6. A. Hurst. Fast synthesis of clock gates from existing logic. International Workshop on Logic Synthesis (IWLS) 2007
7. M. Damiani and G. De Micheli. Observability don't care sets and Boolean relations. Proc. of International Conference on Computer Aided Design (ICCAD) 1990