A test-vector generation methodology for crosstalk noise faults

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2002, Pages 40-47

  Hashempour, H ^a   Kim, Yong Bin ^a   Park, N ^a  

^a OKLAHOMA STATE UNIVERSITY   (United States)

Author keywords

Built in self test; Circuit faults; Circuit simulation; Circuit testing; Clocks; Crosstalk; Delay; Integrated circuit interconnections; Logic design; Wires

Indexed keywords

CHEMICAL ACTIVATION; CIRCUIT SIMULATION; CLOCKS; CROSSTALK; DEFECTS; DESIGN FOR TESTABILITY; FAULT TOLERANCE; INTEGRATED CIRCUIT INTERCONNECTS; INTEGRATED CIRCUIT TESTING; LOGIC CIRCUITS; LOGIC DESIGN; LOGIC DEVICES; VLSI CIRCUITS; WIRE;

CIRCUIT FAULTS; CIRCUIT TESTING; DELAY; INTEGRATED CIRCUIT INTERCONNECTIONS; NOISE CHARACTERIZATION; SATISFIABILITY PROBLEMS; TEST GENERATIONS; TEST VECTOR GENERATIONS;

BUILT-IN SELF TEST;

EID: 51549089131     PISSN: 15505774     EISSN: None     Source Type: Journal    
DOI: 10.1109/DFTVS.2002.1173500     Document Type: Article

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