메뉴 건너뛰기




Volumn , Issue , 2008, Pages 1453-1456

Address Assignment Sensitive Variable Partitioning and scheduling for DSPS with multiple memory banks

Author keywords

Design automation; Memory management; Program compilers; Scheduling

Indexed keywords

DESIGN AUTOMATION; MEMORY BANKS; MEMORY MANAGEMENT; SCHEDULING;

EID: 51449117595     PISSN: 15206149     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICASSP.2008.4517894     Document Type: Conference Paper
Times cited : (13)

References (8)
  • 2
    • 0036058079 scopus 로고    scopus 로고
    • Address assignment combined with scheduling in dsp code generation
    • June
    • Y. Choi and T. Kim. Address assignment combined with scheduling in dsp code generation. In ACM IEEE Design Automation Conference, pages 225-230, June 2002.
    • (2002) ACM IEEE Design Automation Conference , pp. 225-230
    • Choi, Y.1    Kim, T.2
  • 5
    • 0347498863 scopus 로고
    • Synthesis and optimization of digital circuits
    • G. Micheli. Synthesis and optimization of digital circuits. McGraw-Hill, Inc., 1994.
    • (1994) McGraw-Hill, Inc
    • Micheli, G.1
  • 6
    • 84911584312 scopus 로고    scopus 로고
    • Shortest connection networks and some generaliza-toins
    • 36
    • R. Prim. Shortest connection networks and some generaliza-toins. Bell Systems Technical Journal, (36).
    • Bell Systems Technical Journal
    • Prim, R.1
  • 8
    • 1842429024 scopus 로고    scopus 로고
    • Efficient variable partitioning and scheduling for dsp processors with multiple memory modules
    • Q. Zhuge, E. Sha, B. Xiao, and C. Chantrapornchai. Efficient variable partitioning and scheduling for dsp processors with multiple memory modules. IEEE Transaction on Signal Processing, 52:1090-1099, 2003.
    • (2003) IEEE Transaction on Signal Processing , vol.52 , pp. 1090-1099
    • Zhuge, Q.1    Sha, E.2    Xiao, B.3    Chantrapornchai, C.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.