Influence of STI stress on drain current matching in advanced CMOS

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2008, Pages 238-242

  Wils, Nicole ^a   Tuinhout, Hans ^a   Meijer, Maurice ^b  

^a NXP TSMC Research Center   (Netherlands)

^b NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS TECHNOLOGIES; DATA ANALYSIS; TEST STRUCTURES;

DATA STRUCTURES;

EID: 51349149660     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICMTS.2008.4509345     Document Type: Conference Paper

References (8)

1. Gregory Scott et al., "NMOS Drive Current Reduction Caused by Transistor layout and Trench Isolation Induced Stress"; IEDM 1999 Conference Proceedings, pp. 827-830
2. Y. Sheu et al.," Modelling Mechanical Stress Effect on Dopant Diffusion in Scaled MOSFETs"; Transactions on Elec-tron Devices, vol. 52, no.1, January 2005, pp. 30-38
3. P.G. Drennan et al., "Implications of Proximity Effects for Analog Design"; CICC 2006 Conference Proceedings, pp. 169-176
4. Tan et al., "Effect of Shallow Trench Induced Stress on CMOS Transistor Mismatch", ICSE 2004 Conference Pro-ceedings, pp. 189-192
5. Miyamoto et al., "Impact of Reducing STI-Induced Stress on Layout Dependence of MOSFET Characteristics"; Transac-tions on Electron Devices, vol. 51, no.3, March 2004
6. J.A. Croon et al., "A comparison of extraction techniques for threshold voltage mismatch", ICMTS 2002 Conference Proceedings, vol.15, pp.235-239
7. Dragan Manic, "Drift in Silicon Integrated Sensors and Circuits due to Thermo-Mechanical Stresses", Series in Micro systems, Volume 8, Hartung-Gorre (2000)
8. web page: http://www.eigroup.org/cmc/