Effect of shallow trench isolation induced stress on CMOS transistor mismatch

Proceedings ICSE 2004 - 2004 IEEE International Conference on Semiconductor Electronics

Volumn , Issue , 2004, Pages 189-192

  Tan, Philip Beow Yew ^a,b   Kordesch, Albert Victor ^a   Sidek, Othman ^b  

^a SILTERRA MALAYSIA SDN BHD   (Malaysia)

^b SCHOOL OF CHEMICAL ENGINEERING   (Malaysia)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CONDUCTIVITY; SEMICONDUCTOR MATERIALS; SPEECH ANALYSIS; STRESSES;

CMOS TRANSISTORS; INTERNATIONAL CONFERENCES; SEMICONDUCTOR ELECTRONICS; SHALLOW-TRENCH ISOLATION;

TRANSISTORS;

EID: 51349147040     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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6. O. Fujii, H. Yoshimura, R. Hasumi, T. Sanuki, H. Oyamatsu, F. Matsuoka and T. Noguchi, "Modeling of Stress Induced Layout Effect on Electrical Characteristics of Advanced MOSFETs," IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), (2004).
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