Modelling Latency-Insensitive Systems in CSP

Proceedings - 7th International Conference on Application of Concurrency to System Design, ACSD 2007

Volumn , Issue , 2007, Pages 231-232

  Kapoor, Hemangee K ^a  

^a DHIRUBHAI AMBANI INSTITUTE OF INFORMATION AND COMMUNICATION TECHNOLOGY   (India)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 51149112045     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ACSD.2007.54     Document Type: Conference Paper

References (11)

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10. M. Singh and M. Theobald. Generalised Latency-Insensitive Systems for GALS Architectures. In Proc. of FMGALS, 2003.
11. S. Suhaib, D. Mathaikutty, S. Shukla, and D. Berner. Validating Families of Latency Insensitive Protocols. IEEE Trans. on Computers, 55(11): 1391-1401, Nov 2006.