Impact of line-edge roughness on resistance and capacitance of scaled interconnects

Microelectronic Engineering

Volumn 84, Issue 11, 2007, Pages 2733-2737

  Stucchi, M ^a   Bamal, M ^a,b   Maex, K ^b  

^a IMEC   (Belgium)

^b Signal Processing and Data Analytics iMinds Future Health Department   (Belgium)

Author keywords

Interconnect resistance and capacitance; Line edge roughness; Technology scaling

Indexed keywords

APPROXIMATION THEORY; CAPACITANCE; COMPUTER SIMULATION; ELECTRIC RESISTANCE; PARAMETER ESTIMATION;

INTERCONNECT RESISTANCE AND CAPACITANCE; LER PARAMETERS; LINE EDGE ROUGHNESS; TECHNOLOGY SCALING;

OPTICAL INTERCONNECTS;

EID: 34548816990     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2007.05.038     Document Type: Article

References (8)

1. J.A. Croon et al., in: Proceedings of ESSDERC, 2003, pp. 227-230.
2. Leunissen L.H.A., Zhang W., Wu W., and Brongersma S.H. J. Vac. Sci. Technol. B 24 4 (2006) 1859-1862
3. Winkelmeier S., Sarstedt M., Ereken M., Goethals M., and Ronse K. Microelec. Eng. 665 (2001) 57-58
4. Cardinale G.F., Henderson C.C., Goldsmith J.E.M., Mangat P.J.S., Cobb J., and Hector S.D. J. Vac. Sci. Technol. B 17 (1999) 2970-2974
5. Asenov A., et al. IEEE TED 50 5 (2003) 1254-1260
6. Synopsys Raphael Reference Manual, 2006.03.
7. International Technology Roadmap for Semiconductors, 2005 ed. .
8. Travaly Y., et al. J. Microelectron. Eng. 83 11-12 (2006) 2417-2421