-
1
-
-
50949086188
-
-
Altera. Apex redundancy. http://www.altera.com/products/devices/apex/ features/apx-redundancy.html.
-
Apex redundancy
-
-
-
2
-
-
0031362699
-
Defect tolerance on the teramac custom computer
-
W. B. Culbertson, R. Amerson, R. J. Carter, P. Kuekes, and G. Snider. Defect tolerance on the teramac custom computer. In Proc. IEEE Symposium on FPGA-Based Custom Computing Machines (FCCM), page 116, 1997.
-
(1997)
Proc. IEEE Symposium on FPGA-Based Custom Computing Machines (FCCM)
, pp. 116
-
-
Culbertson, W.B.1
Amerson, R.2
Carter, R.J.3
Kuekes, P.4
Snider, G.5
-
3
-
-
50949108664
-
Yield enhancing defect tolerance techniques for FPGAs
-
Submitted to FPL 2007
-
A. Djupdal and P. C. Haddow. Yield enhancing defect tolerance techniques for FPGAs. In FPL 2007, 2007. Submitted to FPL 2007.
-
(2007)
FPL 2007
-
-
Djupdal, A.1
Haddow, P.C.2
-
6
-
-
0031649068
-
Methodologies for tolerating cell and interconnect faults in FPGAs
-
F. Hanchek and S. Dutt. Methodologies for tolerating cell and interconnect faults in FPGAs. IEEE Transactions on Computers, 47(1):15-33, 1998.
-
(1998)
IEEE Transactions on Computers
, vol.47
, Issue.1
, pp. 15-33
-
-
Hanchek, F.1
Dutt, S.2
-
8
-
-
17144442726
-
-
F. Hatori, T. Sakurai, K. Nogami, K. Sawada, M. Takahashi, M. Ichida, M. Uchida, I. Yoshii, Y. Kawahara, T. Hibi, Y. Saeki, H. Muraoga, A. Tanaka, and K. Kanzaki. Introducing redundancy in field programmable gate arrays. In Proc. IEEE Custom Integrated Circuits Conference, pages 7.1.1-7.1.4, 1993.
-
F. Hatori, T. Sakurai, K. Nogami, K. Sawada, M. Takahashi, M. Ichida, M. Uchida, I. Yoshii, Y. Kawahara, T. Hibi, Y. Saeki, H. Muraoga, A. Tanaka, and K. Kanzaki. Introducing redundancy in field programmable gate arrays. In Proc. IEEE Custom Integrated Circuits Conference, pages 7.1.1-7.1.4, 1993.
-
-
-
-
10
-
-
0003029125
-
Evolving hardware with genetic learning: A first step towards building a darwin machine
-
T. Higuchi, T. Niwa, T. Tanaka, H. Iba, H. de Garis, and T. Furuya. Evolving hardware with genetic learning: a first step towards building a darwin machine. In Proc. 2nd int. conf. From animals to animats: simulation of adaptive behavior, pages 417-424, 1993.
-
(1993)
Proc. 2nd int. conf. From animals to animats: Simulation of adaptive behavior
, pp. 417-424
-
-
Higuchi, T.1
Niwa, T.2
Tanaka, T.3
Iba, H.4
de Garis, H.5
Furuya, T.6
-
11
-
-
50949092361
-
-
ITRS. International technology roadmap for semiconductors. Technical report, ITRS, 2005.
-
ITRS. International technology roadmap for semiconductors. Technical report, ITRS, 2005.
-
-
-
-
12
-
-
0032164444
-
Defect tolerance in VLSI circuits: Techniques and yield analysis
-
sep
-
I. Koren and Z. Koren. Defect tolerance in VLSI circuits: Techniques and yield analysis. Proceedings of the IEEE, 86(9):1819-1837, sep 1998.
-
(1998)
Proceedings of the IEEE
, vol.86
, Issue.9
, pp. 1819-1837
-
-
Koren, I.1
Koren, Z.2
-
13
-
-
0032096706
-
Low overhead fault-tolerant FPGA systems
-
J. Lach, W. H. Mangione-Smith, and M. Potkonjak. Low overhead fault-tolerant FPGA systems. IEEE Trans. Very Large Scale Integr. Syst., 6(2):212-221, 1998.
-
(1998)
IEEE Trans. Very Large Scale Integr. Syst
, vol.6
, Issue.2
, pp. 212-221
-
-
Lach, J.1
Mangione-Smith, W.H.2
Potkonjak, M.3
-
15
-
-
1542617054
-
Adaptive methods for growing electronic circuits on an imperfect synthetic matrix
-
N. J. Macias and L. J. K. Durbeck. Adaptive methods for growing electronic circuits on an imperfect synthetic matrix. Biosystems, 73(3):173-204, 2004.
-
(2004)
Biosystems
, vol.73
, Issue.3
, pp. 173-204
-
-
Macias, N.J.1
Durbeck, L.J.K.2
-
16
-
-
35048900225
-
Evolving a self-repairing, self-regulating, french flag organism
-
J. F. Miller. Evolving a self-repairing, self-regulating, french flag organism. In Genetic and Evolutionary Computation (GECCO), pages 129-139, 2004.
-
(2004)
Genetic and Evolutionary Computation (GECCO)
, pp. 129-139
-
-
Miller, J.F.1
-
17
-
-
0000239313
-
Principles in the evolutionary design of digital circuits part i
-
J. F. Miller, D. Job, and V. K. Vassilev. Principles in the evolutionary design of digital circuits part i. Journal of Genetic Programming and Evolvable Machines, 1(1):8-35, 2000.
-
(2000)
Journal of Genetic Programming and Evolvable Machines
, vol.1
, Issue.1
, pp. 8-35
-
-
Miller, J.F.1
Job, D.2
Vassilev, V.K.3
-
18
-
-
50949102538
-
-
overview
-
Xilinx. Xilinx virtex 5 overview. http://www.xilinx.com/products/virtex5/ index.htm.
-
Xilinx virtex
, vol.5
-
-
-
19
-
-
33745841786
-
Defect-tolerant FPGA switch block and connection block with fine-grain redundancy for yield enhancement
-
A. J. Yu and G. G. F. Lemieux. Defect-tolerant FPGA switch block and connection block with fine-grain redundancy for yield enhancement. In Proc. Field Programmable Logic and Applications, pages 255-252, 2005.
-
(2005)
Proc. Field Programmable Logic and Applications
, pp. 255-252
-
-
Yu, A.J.1
Lemieux, G.G.F.2
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