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Volumn , Issue , 2007, Pages 455-462

Evolving redundant structures for reliable circuits - Lessons learned

Author keywords

[No Author keywords available]

Indexed keywords

ARTIFICIAL EVOLUTION; LESSONS LEARNED; SEMICONDUCTOR TECHNOLOGIES;

EID: 50949093813     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/AHS.2007.52     Document Type: Conference Paper
Times cited : (13)

References (19)
  • 1
    • 50949086188 scopus 로고    scopus 로고
    • Altera. Apex redundancy. http://www.altera.com/products/devices/apex/ features/apx-redundancy.html.
    • Apex redundancy
  • 3
    • 50949108664 scopus 로고    scopus 로고
    • Yield enhancing defect tolerance techniques for FPGAs
    • Submitted to FPL 2007
    • A. Djupdal and P. C. Haddow. Yield enhancing defect tolerance techniques for FPGAs. In FPL 2007, 2007. Submitted to FPL 2007.
    • (2007) FPL 2007
    • Djupdal, A.1    Haddow, P.C.2
  • 6
    • 0031649068 scopus 로고    scopus 로고
    • Methodologies for tolerating cell and interconnect faults in FPGAs
    • F. Hanchek and S. Dutt. Methodologies for tolerating cell and interconnect faults in FPGAs. IEEE Transactions on Computers, 47(1):15-33, 1998.
    • (1998) IEEE Transactions on Computers , vol.47 , Issue.1 , pp. 15-33
    • Hanchek, F.1    Dutt, S.2
  • 8
    • 17144442726 scopus 로고    scopus 로고
    • F. Hatori, T. Sakurai, K. Nogami, K. Sawada, M. Takahashi, M. Ichida, M. Uchida, I. Yoshii, Y. Kawahara, T. Hibi, Y. Saeki, H. Muraoga, A. Tanaka, and K. Kanzaki. Introducing redundancy in field programmable gate arrays. In Proc. IEEE Custom Integrated Circuits Conference, pages 7.1.1-7.1.4, 1993.
    • F. Hatori, T. Sakurai, K. Nogami, K. Sawada, M. Takahashi, M. Ichida, M. Uchida, I. Yoshii, Y. Kawahara, T. Hibi, Y. Saeki, H. Muraoga, A. Tanaka, and K. Kanzaki. Introducing redundancy in field programmable gate arrays. In Proc. IEEE Custom Integrated Circuits Conference, pages 7.1.1-7.1.4, 1993.
  • 11
    • 50949092361 scopus 로고    scopus 로고
    • ITRS. International technology roadmap for semiconductors. Technical report, ITRS, 2005.
    • ITRS. International technology roadmap for semiconductors. Technical report, ITRS, 2005.
  • 12
    • 0032164444 scopus 로고    scopus 로고
    • Defect tolerance in VLSI circuits: Techniques and yield analysis
    • sep
    • I. Koren and Z. Koren. Defect tolerance in VLSI circuits: Techniques and yield analysis. Proceedings of the IEEE, 86(9):1819-1837, sep 1998.
    • (1998) Proceedings of the IEEE , vol.86 , Issue.9 , pp. 1819-1837
    • Koren, I.1    Koren, Z.2
  • 15
    • 1542617054 scopus 로고    scopus 로고
    • Adaptive methods for growing electronic circuits on an imperfect synthetic matrix
    • N. J. Macias and L. J. K. Durbeck. Adaptive methods for growing electronic circuits on an imperfect synthetic matrix. Biosystems, 73(3):173-204, 2004.
    • (2004) Biosystems , vol.73 , Issue.3 , pp. 173-204
    • Macias, N.J.1    Durbeck, L.J.K.2
  • 16
    • 35048900225 scopus 로고    scopus 로고
    • Evolving a self-repairing, self-regulating, french flag organism
    • J. F. Miller. Evolving a self-repairing, self-regulating, french flag organism. In Genetic and Evolutionary Computation (GECCO), pages 129-139, 2004.
    • (2004) Genetic and Evolutionary Computation (GECCO) , pp. 129-139
    • Miller, J.F.1
  • 18
    • 50949102538 scopus 로고    scopus 로고
    • overview
    • Xilinx. Xilinx virtex 5 overview. http://www.xilinx.com/products/virtex5/ index.htm.
    • Xilinx virtex , vol.5
  • 19
    • 33745841786 scopus 로고    scopus 로고
    • Defect-tolerant FPGA switch block and connection block with fine-grain redundancy for yield enhancement
    • A. J. Yu and G. G. F. Lemieux. Defect-tolerant FPGA switch block and connection block with fine-grain redundancy for yield enhancement. In Proc. Field Programmable Logic and Applications, pages 255-252, 2005.
    • (2005) Proc. Field Programmable Logic and Applications , pp. 255-252
    • Yu, A.J.1    Lemieux, G.G.F.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.