3D CMOS integration: Introduction of dynamic coupling and application to compact and robust 4T SRAM

Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT

Volumn , Issue , 2008, Pages 281-284

  Batude, P ^a   Jaud, M A ^c   Thomas, O ^c   Clavelier, L ^c   Pouydebasque, A ^c   Vinet, M ^c   Deleonibus, S ^c   Amara, A ^b  

^a CEA LETI   (France)

^b Institut Superieur d'Electronique de Paris ISEP   (France)

^c NONE

Author keywords

3D IC; Dynamic threshold voltage modification; Sequential three dimensional integration; SRAM

Indexed keywords

3-DIMENSIONAL; 3D IC; 4T SRAM; CMOS INTEGRATION; DYNAMIC COUPLINGS; DYNAMIC THRESHOLD; DYNAMIC THRESHOLD VOLTAGE MODIFICATION; INNOVATIVE STRUCTURES; INTEGRATED CIRCUIT DESIGN; INTEGRATION TECHNOLOGIES; INTER LAYER DIELECTRIC; INTERNATIONAL CONFERENCES; SEQUENTIAL THREE DIMENSIONAL INTEGRATION; SRAM;

ELECTRONICS INDUSTRY; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATION; TECHNOLOGY;

INTEGRATED CIRCUITS;

EID: 50849096284     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICICDT.2008.4567296     Document Type: Conference Paper

References (9)

1. M. Yamaoka, et al, "Low power SRAM Menu for SOC application Using Yin-Yang-Feedback Memoiy Cell Technology", VLSI Cir. Digest, pp 288-291, June 2004.
2. S. Mukhopadhyay et al, "Device design and optmisation methodology for leakage and varaibility reduction in sub-45nm FD/SOI SRAM" vol55,no1, pp 152-162, Jan 2008.
3. P. Lindner et al, "Advances in aligned wafer bonding for 3D interconnects", IMAPS European Symposium, June 2002.
4. F. Andrieu et al,"Impact of Mobility Boosters (XsSOI, CESL, TiN gate) on the Performance of 〈100〉 or 〈110〉 oriented FDSOI cMOSFETs for the 32nm Node", Symp. of VLSI Technology, pp. 50-1, 2007.
5. A. Lauwers et al, Materials Science and Engineering B Volumes 114-115, Dec 2004, pp 29-41.
6. 3 SRAM technology with doubly stacked Si layers, peripheral only CoSix layers and tungsten shunt" Symp. of VLSI Technology, pp. 82-3, 2007.
7. J. Feng et al, "Integration of germanium-on-insulator and silicon MOSFETs on a silicon substrate", Electronic device letters, vol 27 no 1 pp911-913, Nov 2006.
8. O. Thomas et al, "An. SOI 4 Transistors Self-Refresh Ultra-Low Voltage memory cell", ISCAS, Bangkok, May 2003.
9. K. Takeda, et al., "A 16Mb 400MHz Loadless CMOS Four-Transistor SRAM Macro", ISSCC, pp. 264-265, Feb 2000