Phase-change memory technology with self-aligned μTrench cell architecture for 90 nm node and beyond

Solid-State Electronics

Volumn 52, Issue 9, 2008, Pages 1467-1472

  Pirovano, A ^a   Pellizzer, F ^a   Tortorelli, I ^a   Rigano A ^a   Harrigan, R ^b   Magistretti, M ^a   Petruzza, P ^a   Varesi, E ^a   Redaelli, A ^a   Erbetta, D ^a   Marangon, T ^a   Bedeschi, F ^a   Fackenthal, R ^b   Atwood, G ^b   Bez, R ^a  

^a STMICROELECTRONICS   (Italy)

^b INTEL CORPORATION   (United States)

Author keywords

Chalcogenide; PCM; Phase change memories

Indexed keywords

BIPOLAR TRANSISTORS; CMOS INTEGRATED CIRCUITS; DATA STORAGE EQUIPMENT; LEAKAGE CURRENTS; MOSFET DEVICES; PULSE CODE MODULATION; TECHNOLOGY; TRANSISTORS; TUNNEL DIODES;

90NM NODE; BIPOLAR JUNCTION TRANSISTOR; CELL ARCHITECTURES; CHALCOGENIDE; DIMENSIONAL CONTROL; HIGH-DENSITY; INTEGRATION PROCESSES; PCM; PHASE-CHANGE MEMORIES; PHASE-CHANGE MEMORY TECHNOLOGY; PROGRAMMING CURRENTS; PROPOSED ARCHITECTURES; SELF-ALIGNED; SELF-ALIGNED PATTERNING;

PHASE CHANGE MEMORY;

EID: 50349090675     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2008.04.031     Document Type: Article

References (11)

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