Scalable PEEC-SPICE modelling for EMI analysis of power electronic packages and subsystems

Proceedings of the Electronic Packaging Technology Conference, EPTC

Volumn , Issue , 2006, Pages 871-878

  Cottet, Didier ^a   Paakkinen, Mikko ^a  

^a ABB SWITZERLAND LTD   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; COMPUTATIONAL METHODS; ELECTRIC IMPEDANCE MEASUREMENT; ELECTRIC NETWORK ANALYSIS; ELECTROMAGNETIC COMPATIBILITY; ELECTROMAGNETIC PULSE; ELECTROMAGNETISM; ELECTRONIC EQUIPMENT MANUFACTURE; ELECTRONICS PACKAGING; EQUIVALENT CIRCUITS; MATRIX ALGEBRA; NETWORKS (CIRCUITS); SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE STRUCTURES; TECHNOLOGY;

COMPONENT PINS; CROSS COUPLINGS; DEVICE MODELLING; ELECTROMAGNETIC INTERFERENCE ANALYSIS; ELECTRONIC PACKAGING; EMI ANALYSIS; IMPEDANCE MATRICES; LEVEL OF DETAILS; PACKAGING TECHNOLOGIES; PARASITIC IMPEDANCE; PARTIAL-ELEMENT-EQUIVALENT-CIRCUIT METHOD; POWER ELECTRONIC SYSTEMS; SCALING METHODS; SUB-CIRCUITS; SUBSYSTEM MODELS; SYSTEM COMPONENTS; TURN-OFF;

SPICE;

EID: 50249139168     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2006.342827     Document Type: Conference Paper

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