Highly reliable interface of self-aligned CuSiN process with low-k SiC barrier dielectric (k=3.5) for 65nm node and beyond

2006 International Interconnect Technology Conference, IITC

Volumn , Issue , 2006, Pages 125-127

  Usami, T ^a   Ide, T ^b   Kakuhara, Y ^a   Ajima, Y ^a   Ueno, K ^a   Maruyama, T ^a   Yu, Y ^b   Apen, E ^c   Chattopadhyay, K ^b   Van Schravendijk, B ^c   Oda, N ^a   Sekine, M ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b Novellus Systems Inc   (United States)

^c NOVELLUS SYSTEMS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MANGANESE COMPOUNDS; SILICON CARBIDE;

65-NM NODES; BARRIER DIELECTRICS; ELECTRICAL FAILURES; INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE; PERFORMANCE ENHANCEMENTS; PLASMA PRE-TREATMENT; SELF-ALIGNED;

TECHNOLOGY;

EID: 50249097333     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2006.1648665     Document Type: Conference Paper

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