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1
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0032202596
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High-level power modeling, estimation, and optimization
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November
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E. Macii, M. Pedram, F. Somenzi, "High-Level Power Modeling, Estimation, and Optimization," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, No. 11, November 1998.
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(1998)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.17
, Issue.11
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Macii, E.1
Pedram, M.2
Somenzi, F.3
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2
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0028715171
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Saving power in the control path of embedded processors
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Winter
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C. L. Su, C. Y. Tsui, A. M. Despain, "Saving Power in the Control Path of Embedded Processors," IEEE Design and Test of Computers, Vol. 11, No. 4, pp. 24-30, Winter 1994.
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Su, C.L.1
Tsui, C.Y.2
Despain, A.M.3
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3
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35048834531
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Bus-invert coding for low-power i/o
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January
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M. R. Stan, W. P. Burleson, "Bus-Invert Coding for Low-Power I/O," IEEE Transactions on VLSI Sys-tems, Vol. 3, No. 1, pp. 49-58, January 1995.
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IEEE Transactions on VLSI Sys-Tems
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Stan, M.R.1
Burleson, W.P.2
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4
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0030644909
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Asymptotic zero-transition activity encod-ing for address busses in low-power microprocessor-based systems
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March
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L. Benini, G. De Micheli, E. Macii, D. Sciuto, C. Sil-vano, "Asymptotic Zero-Transition Activity Encod-ing for Address Busses in Low-Power Microprocessor-Based Systems," GLS-VLSI-97: IEEE/ACM Great Lakes Symposium on VLSI, pp. 77-82, March 1997.
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(1997)
GLS-VLSI-97: IEEE/ACM Great Lakes Symposium on VLSI
, pp. 77-82
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Benini, L.1
De Micheli, G.2
Macii, E.3
Sciuto, D.4
Sil-Vano, C.5
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5
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84893775814
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Address bus encoding techniques for system-level power optimization
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Febru-ary
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L. Benini, G. De Micheli, E. Macii, D. Sciuto, C. Sil-vano, "Address Bus Encoding Techniques for System-Level Power Optimization", DATE-98: IEEE Design Automation and Test in Europe, pp. 861-866, Febru-ary 1998.
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(1998)
DATE-98: IEEE Design Automation and Test in Europe
, pp. 861-866
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Benini, L.1
De Micheli, G.2
Macii, E.3
Sciuto, D.4
Sil-Vano, C.5
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6
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0032300757
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Reducing power consumption of core-based systems by address bus encoding
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December
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L. Benini, G. De Micheli, E. Macii, M. Poncino, S. Quer, "Reducing Power Consumption of Core-Based Systems By Address Bus Encoding", IEEE Transac-tions on VLSI Systems, Vol. 6, No. 4, pp. 554-562, December 1998.
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(1998)
IEEE Transac-Tions on VLSI Systems
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, pp. 554-562
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Benini, L.1
De Micheli, G.2
Macii, E.3
Poncino, M.4
Quer, S.5
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7
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0032287846
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Working-zone encoding for reducing the energy in microproces-sor address buses
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December
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E. Musoll, T. Lang, J. Cortadella, "Working-Zone Encoding for Reducing the Energy in Microproces-sor Address Buses," IEEE Transactions on VLSI Sys-tems, Vol. 6, No. 4, pp. 568-572, December 1998.
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IEEE Transactions on VLSI Sys-Tems
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, pp. 568-572
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Musoll, E.1
Lang, T.2
Cortadella, J.3
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8
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0032660358
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Synthesis of low-overhead interfaces for power-ecient communication over wide buses
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June
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L. Benini, A. Macii, E. Macii, M. Poncino, R. Scarsi, "Synthesis of Low-Overhead Interfaces for Power-Ecient Communication over Wide Buses", DAC-36: ACM/IEEE Design Automation Confer-ence, June 1999, pp. 128-133.
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DAC-36: ACM/IEEE Design Automation Confer-Ence
, pp. 128-133
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Benini, L.1
Macii, A.2
Macii, E.3
Poncino, M.4
Scarsi, R.5
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9
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0001868375
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Global communication and memory op-timizing transformations for low power design
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April
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S. Wuytack, F. Catthoor, L. Nachtergaele, H. De Man, "Global Communication and Memory Op-timizing Transformations for Low Power Design," IWLPD-94: ACM/IEEE International Workshop on Low Power Design, pp. 203-208, April 1994.
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IWLPD-94: ACM/IEEE International Workshop on Low Power Design
, pp. 203-208
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Wuytack, S.1
Catthoor, F.2
Nachtergaele, L.3
De Man, H.4
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12
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0030383420
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Power exploration for data dominated video applications
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August
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S. Wuytack, F. Catthoor, L. Nachtergaele, H. De Man, "Power Exploration for Data Dominated Video Applications," ISLPED-96: ACM/IEEE Inter-national Symposium on Low Power Electronics and Design, pp. 359-364, August 1996.
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ISLPED-96: ACM/IEEE Inter-National Symposium on Low Power Electronics and Design
, pp. 359-364
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Wuytack, S.1
Catthoor, F.2
Nachtergaele, L.3
De Man, H.4
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13
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0032303141
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Formalized methodology for data reuse ex-ploration in hierarchical memory mappings
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December
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J. P. Diguet, S. Wuytack, F. Catthoor, H. De Man, "Formalized Methodology for Data Reuse Ex-ploration in Hierarchical Memory Mappings," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 6, No. 4, pp. 529-537, December 1998.
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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, pp. 529-537
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Diguet, J.P.1
Wuytack, S.2
Catthoor, F.3
De Man, H.4
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14
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0002945337
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Embedded con-trol problems, thumb and the arm7tdmi
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October
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S. Segars, K. Clarke, L. Goudge, "Embedded Con-trol Problems, Thumb and the ARM7TDMI," IEEE Micro, Vol. 15, No. 5, pp. 22-30, October 1995.
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IEEE Micro
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Segars, S.1
Clarke, K.2
Goudge, L.3
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15
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0030650199
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An object code compression approach to embedded processors
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August
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Y. Yoshida, B.-Y. Song, H. Okuhata, T. Onoye, I. Shirakawa, "An Object Code Compression Approach to Embedded Processors," ISLPED-98: ACM/IEEE International Symposium on Low Power Electronics and Design, pp. 265-268, August 1997.
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ISLPED-98: ACM/IEEE International Symposium on Low Power Electronics and Design
, pp. 265-268
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Yoshida, Y.1
Song, B.-Y.2
Okuhata, H.3
Onoye, T.4
Shirakawa, I.5
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16
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0033359508
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Se-lective instruction compression for memory en-ergy reduction in embedded systems
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August
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L. Benini, A. Macii, E. Macii, M. Poncino, "Se-lective Instruction Compression for Memory En-ergy Reduction in Embedded Systems", ISLPED-99: ACM/IEEE 1999 International Symposium on Low Power Electronics and Design, August 1999.
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(1999)
ISLPED-99: ACM/IEEE 1999 International Symposium on Low Power Electronics and Design
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Benini, L.1
Macii, A.2
Macii, E.3
Poncino, M.4
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