|
|
Volumn 5, Issue 9, 2008, Pages 2729-2732
|
|
GaAs high-k dielectric metal-insulator-semiconductor structure having silicon interface control layer
a
|
|
Author keywords
[No Author keywords available]
|
|
Indexed keywords
AIR-EXPOSURE;
BUFFER FILMS;
CAPACITANCE VOLTAGE;
DOUBLE LAYERS;
EX SITU;
FERMI LEVEL PINNING;
GAAS;
GAAS SURFACES;
GATE STACKS;
HETERO INTERFACES;
HIGH-K DIELECTRIC;
IN-SITU;
INTERFACE CONTROL LAYER;
INTERFACE STATE DENSITY;
METAL INSULATOR SEMICONDUCTOR STRUCTURES;
METAL-INSULATOR-SEMICONDUCTORS;
MIS CAPACITORS;
MIS STRUCTURE;
SILICON INTERFACE;
ULTRA-THIN;
CAPACITANCE;
CRYSTAL GROWTH;
GALLIUM ALLOYS;
GALLIUM ARSENIDE;
GEL PERMEATION CHROMATOGRAPHY;
HAFNIUM COMPOUNDS;
METAL ANALYSIS;
METAL INSULATOR BOUNDARIES;
MIS DEVICES;
MOLECULAR BEAM EPITAXY;
MOLECULAR BEAMS;
RAPID THERMAL ANNEALING;
RAPID THERMAL PROCESSING;
SEMICONDUCTING GALLIUM;
SEMICONDUCTING SILICON;
SEMICONDUCTOR INSULATOR BOUNDARIES;
SILICON NITRIDE;
SILICON OXIDES;
SWITCHING CIRCUITS;
X RAY PHOTOELECTRON SPECTROSCOPY;
SEMICONDUCTING SILICON COMPOUNDS;
|
|
EID: 49749151305
PISSN: 18626351
EISSN: 16101642
Source Type: Journal
DOI: 10.1002/pssc.200779208 Document Type: Conference Paper |
|
Times cited : (2)
|
|
References (8)
|
