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Volumn , Issue , 2008, Pages 734-737

A design model for random process variability

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT DESIGNS; DESIGN MODELING; DESIGN VARIABLES; ELECTRONIC DESIGNS; INTERNATIONAL SYMPOSIUM; NEW APPROACHES; OPERATING POINTS; POSYNOMIAL; PROCESS VARIABILITY; PROCESS VARIATIONS;

EID: 49749125050     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2008.4479829     Document Type: Conference Paper
Times cited : (10)

References (11)
  • 1
    • 39749152930 scopus 로고    scopus 로고
    • Impact of Layout on 90nm CMOS Process Parameter Fluctuations
    • L. T. Pang and B. Nikolic, Impact of Layout on 90nm CMOS Process Parameter Fluctuations, VLSI Symposium, 2006.
    • (2006) VLSI Symposium
    • Pang, L.T.1    Nikolic, B.2
  • 3
    • 39749142750 scopus 로고    scopus 로고
    • A Test Structure for Characterizing Local Device Mismatches
    • K. Agarwal, F. Liu, C. Mcdowell et al., A Test Structure for Characterizing Local Device Mismatches, VLSI Symposium, 2006.
    • (2006) VLSI Symposium
    • Agarwal, K.1    Liu, F.2    Mcdowell, C.3
  • 8
    • 36348972210 scopus 로고
    • Alpha-Power Law Mosfet Model and its Applications to CMOS Inverter Delay and Other Formulas
    • T. Sakurai and R. Newton, Alpha-Power Law Mosfet Model and its Applications to CMOS Inverter Delay and Other Formulas, IEEE JSSC, 1990.
    • (1990) IEEE JSSC
    • Sakurai, T.1    Newton, R.2
  • 9
    • 49749113718 scopus 로고
    • Statistical Modeling of Device Mismatch for Analog MOS Integrated Circuits
    • C. Michael and M. Ismail, Statistical Modeling of Device Mismatch for Analog MOS Integrated Circuits, IEEE JSSC, 1992.
    • (1992) IEEE JSSC
    • Michael, C.1    Ismail, M.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.