Long wires and asynchronous control

Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems

Volumn 10, Issue , 2004, Pages 240-249

  Ho, Ron ^a   Gainsley, Jon ^a   Drost, Robert ^a  

^a SUN MICROSYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; COSTS; DATA REDUCTION; INTERFACES (COMPUTER); THROUGHPUT; WIRE;

ASYNCHRONOUS CONTROL; MODULAR MACHINES; THROUGHPUT COSTS;

INTEGRATED CIRCUITS;

EID: 2942689688     PISSN: 15228681     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Conference Paper

References (10)

1. K. Mai et al, "Smart Memories: A Modular Reconfigurable Architecture," Proc. Int'l Symposium on Computer Architecture, pp. 161-71, June 2000.
2. M. Taylor et al., "A 16-Issue Multiple Program Counter Microprocessor with Point-to-Point Scalar Operand Networks," IEEE Int'l Solid-State Circuits Conference, pp. 170-1, February 2003.
3. S. Keckler et al., "A Wire-Delay Scalable Microprocessor Architecture for High-Performance Systems," IEEE Int'l Solid-State Circuits Conference, pp. 168-9, February 2003.
4. R. Ho, et al., "The Future of Wires," Proceedings of the IEEE, Vol. 89, Issue 4, pp. 490-504, April 2001.
5. H. Bakoglu, Circuits, Interconnections and Packaging for VLSI, Addison-Wesley, 1990.
6. I. Sutherland et al., "GasP: A Minimal FIFO Control," Proceedings, IEEE Int'l Symposium on Asynchronous Circuits and Systems, March 2001.
7. M. Horowitz, 'Timing Models for MOS Circuits," Ph.D. Thesis, Stanford University, 1983.
8. I. Sutherland, "Micropipelines," Communications of the ACM, Volume 32, No. 6, pp. 720-38, June 1989.
9. J. Ebergen et al., "Transistor Sizing: How To Control The Speed and Energy Consumption of a Circuit," Proceedings, IEEE Int'l Symposium on Asynchronous Circuits and Systems, April 2004.
10. R. Ho et al., "Efficient On-Chip Global Interconnect," Digest of Technical Papers, IEEE Int'l Symposium on VLSI Circuits, pp. 271-4, June 2003.