A 256Mb synchronous-burst DDR SRAM with hierarchical bit-line architecture for mobile applications

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Suh, Y H ^a   Nam, H Y ^a   Kang, S B ^a   Choi, B G ^a   Mo, H S ^a   Han, G H ^a   Shin, H K ^a   Jung, W R ^a   Lim, H ^a   Kwak, C K ^a   Byun, H G ^a  

^a Samsung Advanced Institute of Technology (SAIT)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 25844497130     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. 2, and SSTFT for Ultra High Density SRAM," Symp. on VLSI Tech. Dig., pp.228-229, June, 2004.
2. A. Karandikar et al., "Low Power SRAM Design using Hierarchical Bit-Line Approach," ICCD Proc., pp.82-88, Oct., 1998.
3. H. J. An et al., "64Mb Mobile S3 RAM with SDPS and MCBS for High Density and Low Power SRAM," Symp. on VLSI Circuit Dig., pp.282-283, Jun., 2004.