A 750MHz 144Mb cache DRAM LSI with speed scalable design and programmable at-speed function-array BIST

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages 457-459+507

  Sakakibara, Hideki ^a   Nakayama, Michiaki ^a   Kusunoki, Mitsugu ^a   Kurita, Kohzaburo ^a   Otori, Hiroshi ^a   Hasegawa, Masatoshi ^a   Iwahashi, Satoshi ^a   Higeta, Keiichi ^a   Hanashima, Toshiyuki ^a   Hayashi, Hideki ^a   Kuchimachi, Kazuharu ^b   Uehara, Katsutoshi ^b   Nishiyama, Takashi ^b   Kume, Masaji ^b   Miyamoto, Kazuhisa ^b   Kamada, Eiki ^b  

^a HITACHI LTD   (Japan)

^b Enterprise Server Division   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); BUFFER STORAGE; BUILT-IN SELF TEST; DYNAMIC RANDOM ACCESS STORAGE; INTEGRATED CIRCUIT TESTING; PHASE LOCKED LOOPS;

DIFFERENTIAL SENSE AMPLIFIER; SELF INTEGRATED TEST FOR ARRAY AND FUNCTION; SYNCRHONOUS RANDOM ACCESS MEMORY;

LSI CIRCUITS;

EID: 0038645160     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. J. Barth et al., "A 300MHz Multi-Banked eDRAM Macro Featuring GND Sense, Bit-Line Twisting and Direct Reference Cell Write," ISSCC Digest of Technical Papers, pp. 156-157, 2002.
2. M. Nakayama et al., "A 16MB cache DRAM LSI with internal 35.8GB/s memory bandwidth for simultaneous read and write operation," ISSCC Digest of Technical Papers, pp. 398-399, 2000.
3. Y. Yokoyama et al., "A 1.8-V Embedded 18-Mb DRAM Macro with a 9-ns RAS Access Time and Memory-Cell Area Efficiency of 33%," IEEE Journal of Solid-State Circuits, vol. 36, no. 3, pp. 503-509, 2001.