A SRAM core architecture with adaptive cell bias scheme

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2006, Pages 128-129

  Yu, Hak Soo ^a   Kim, Nam Seog ^a   Son, Young Jae ^a   Kim, Yong Goel ^a   Kim, Hyo Chang ^a   Cho, Uk Rae ^a   Byun, Hyun Geun ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE SYSTEMS; COMPUTER ARCHITECTURE; OPTIMAL SYSTEMS; PARAMETER ESTIMATION;

ADAPTIVE CELL; CELL BIAS SCHEME; LESS PROCESS VARIATION;

STATIC RANDOM ACCESS STORAGE;

EID: 39749173129     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Y. Takeyama et al, VLSI Symp. Dig.,pp. 166-167,2005
2. C. H. Kim et al, VLSI Symp. Dig.,pp.250-251,2004
3. S.-M. Jung et al, VLSI Symp. Dig.,pp.220-221,2005
4. A.J. Bhavnagarwala et al, JSSC,vol.36, pp.658-665,Apr. 2001