Microscopic RF noise simulation and noise source modeling in 50 nm gate length CMOS

2004 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems: Digest of Papers

Volumn , Issue , 2004, Pages 123-126

  Niu, Guofu ^a   Cui, Yan ^a   Taylor, Stewart S ^b  

^a AUBURN UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; CORRELATION METHODS; DOPING (ADDITIVES); HYDRODYNAMICS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; SPURIOUS SIGNAL NOISE;

BIASING CURRENT; NOISE SIMULATION; NOISE SOURCES; POSPIESZALSKI'S MODEL;

CMOS INTEGRATED CIRCUITS;

EID: 20344407789     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

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2. A. van der Ziel, "Noise in Solid-State Devices and Circuits," John Wiley & Sons, 1986.
3. M. W. Pospieszalski, "Modeling of Noise Parameters of MESFET's and MODFET's and Their Frequency and Temperature Dependence," IEEE Transactions on Microwave Theory and Techniques, vol. 37, pp. 508-509, Sep 1989.
4. D. Becher, G. Banerjee, R. Basco, C. Hung, K. Kuhn, Wei-Kai Shih, "Noise Performance of 90 nm CMOS Technology," Tech. Digest IEEE MTT-S, 2004.
5. H. Hillbrand and P. Russer, "An efficient method for computer aided noise analysis of linear networks," IEEE Trans. Circuits and Systems. vol. 23, pp. 235-238, 1976.