Design and optimisation of a high current, high frequency monolithic buck converter

Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC

Volumn , Issue , 2008, Pages 1472-1476

  Hannon, Jason ^a   O'Sullivan, Dara ^a   Foley, Raymond ^a   Griffiths, James ^a   McCarthy, Kevin G ^a   Egan, Michael G ^a  

^a UNIVERSITY COLLEGE CORK   (Ireland)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC EQUIPMENT; EXHIBITIONS;

BUCK CONVERTERS; DESIGN ISSUES; DETAILED DESIGN; HIGH CURRENTS; HIGH FREQUENCIES; OPTIMISATION; OPTIMUM POWER; POINT-OF-LOAD; POWER DEVICES; POWER LOSSES;

POWER ELECTRONICS;

EID: 49249107096     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APEC.2008.4522918     Document Type: Conference Paper

References (12)

1. B. Masserant, E. Beans, and T. Stuart, "A study of volume versus frequency for soft switching IGBT converters," Aerospace and Electronic Systems, IEEE Transactions on, vol. 31, no. 1, pp. 280-287, Jan 1995.
2. S.-G. Yoon, J.-M. Lee, j.-H. Park, I.-K. Lee, and B. Cho, "A frequency controlled bi-directional synchronous rectifier converter for HEV using super capacitor," IEEE Power Electronics Specialists Conference, pp. 135-140, 2004.
3. V. Kursun, S. G. Narendra, V. K. De, and E. G. Friedman, "Low Voltage Swing Monolithic DC-DC Conversion," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 51, pp. 241-248, May 2004.
4. S. Mappus, "Predictive gate drive boosts synchronus DC/DC power converter efficiency," Texas Instruments, 2003.
5. C. Mitter, "Device considerations for high current, low voltage synchronous buck regulators (SBR)," in WESCON/97. Conference Proceedings, November 1997, pp. 281 - 288.
6. Y. Ren, M. Xu, J. Zhou, and F. Lee, "Analytical loss model of power MOSFET," in Power Electronics, IEEE Transactions on, March 2006, pp. 310-319.
7. S. Chen, O. Trescases, and W. T. Ng, "Fast dead-time locked loops for a high-efficiency microprocessor-load ZVS-QSW DC/DC converter," in Electron Devices and Solid-State Circuits, 2003 IEEE Conference on, 16-18 Dec 2003, pp. 391 - 394.
8. N. Li, G. Haviland, and A. Tuszynski, "CMOS tapered buffer," Solid-State Circuits, IEEE Journal of, vol. 25, no. 4, pp. 1005-1008, Aug 1990.
9. C. Prunty and L. Gal, "Optimum Tapered Buffer," Solid-State Circuits, IEEE journal of, vol. 21, no. 1, pp. 118-119, Jan 1992.
10. K. Hedenstierna, N.; Jeppson, "Comments on the optimum CMOS tapered buffer problem," Solid-State Circuits, IEEE Journal of, 21-24 May 1994.
11. R. J. Baker, CMOS Circuit Design, Layout and Simulation. Wiley, 2005.
12. G.Villar, E.Alarcon, J.Madrenas, F.Guinjoan, and A. Poveda, "Energy optimization of tapered buffers for cmos on-chip switching power converters," in Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium, vol. 5, 23-26 May 2005, pp. 4453-4456.