Comments on the Optimum CMOS Tapered Buffer Problem

IEEE Journal of Solid-State Circuits

Volumn 29, Issue 2, 1994, Pages 155-158

  Hedenstierna, Nils ^a   Jeppson, Kjell O ^a  

^a CHALMERS UNIVERSITY OF TECHNOLOGY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

MICROELECTRONICS; MICROPROCESSOR CHIPS; SOLID STATE DEVICES; VLSI CIRCUITS;

CHIP SHRINKING; OPTIMUM TAPERING; SOLID STATE CIRCUITS; TAPERED BUFFER;

CMOS INTEGRATED CIRCUITS;

EID: 0028371528     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.272124     Document Type: Article

References (7)

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3. R. C. Jaeger, “Comments on An optimized output stage for MOS integrated circuits” IEEE J. Solid-State Circuits, vol. SC-10, pp. 185-186, 1975.
4. A. Kanuma, “CMOS circuit optimization,” Solid-State Electronics, vol. 26, pp. 47-58, 1983.
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7. H. J. M. Veendrick, “Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits,” IEEE J. Solid-State Circuits, vol. SC-19, pp. 468-474, 1984.