Optimum Tapered Buffer

IEEE Journal of Solid-State Circuits

Volumn 27, Issue 1, 1992, Pages 118-119

  Prunty, Craig ^a   Gal, Laszlo ^a  

^a Unisys   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; INTEGRATED CIRCUITS, CMOS;

BICMOS BUFFERS; BUFFER DELAYS; CMOS BUFFER TAPERING RULE; SPLIT CAPACITANCE BUFFER; TAPERING FACTOR;

ELECTRONIC CIRCUITS, BUFFER;

EID: 0026626797     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.109565     Document Type: Article

References (4)

1. C. Mead and L. Conway, Introduction to VLSI Systems. Reading, MA: Addison-Wesley, 1980.
2. M. Nemes, “Driving large capacitances in MOS LSI systems,” IEEE J. Solid-State Circuits, vol. SC-19, no. 1, pp. 159–161, Feb. 1984.
3. N. C. Lin, G. L. Haviland, and A. A. Tuszynsky, “CMOS tapered buffer,” IEEE J. Solid-State Circuits, vol. 25, no. 4, pp. 1005–1008, Aug. 1990.
4. H. J. M. Veendrick, “Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits,” IEEE J. Solid-State Circuits, vol. SC-19, no. 4, pp. 468–474, Aug. 1984.