CMOS Tapered Buffer

IEEE Journal of Solid-State Circuits

Volumn 25, Issue 4, 1990, Pages 1005-1008

  Li, N C ^a   Haviland, Gene L ^b   Tuszynski, A A ^c  

^a NORTHEASTERN UNIVERSITY   (United States)

^b Naval Command   (United States)

^c SAN DIEGO STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC NETWORKS--EQUIVALENT CIRCUITS; INTEGRATED CIRCUITS, CMOS; LOGIC DEVICES;

CMOS TAPERED BUFFER; SPLIT-CAPACITOR MODEL; TAPERED INVERTERS;

ELECTRONIC CIRCUITS, BUFFER;

EID: 0025477321     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.58293     Document Type: Article

References (12)

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