Energy optimization of tapered buffers for CMOS on-chip switching power converters

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 4453-4456

  Villar, G ^a   Alarcon E ^a   Madrenas, J ^a   Guinjoan, F ^a   Poveda, A ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY OPTIMIZATION; GATE DRIVERS; HIGH FREQUENCY HF; LINEAR RELATION; ON-CHIP SWITCHING POWER CONVERTER; OPTIMIZED DESIGNS; PMOS TRANSISTORS; POWER CONSUMPTION; POWER MOSFET; RISETIME; STANDARD CMOS TECHNOLOGY; SWITCHING LOSS; TAPERING FACTORS; TRANSISTOR-LEVEL SIMULATION;

CMOS INTEGRATED CIRCUITS; MOSFET DEVICES; POWER CONVERTERS;

SWITCHING;

EID: 49249137785     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465620     Document Type: Conference Paper

References (10)

1. Hung Chang Lin, Loren W. Linholm, "An Optimized Output Stage for MOS Integrated Circuits", IEEE Journal Of Solid-State Circuits, Vol. SC-10, No.2, pp. 106-109, April 1975
2. Richard C. Jaeger, "Comments on "An Optimized Output Stage for MOS Integrated Circuits"", IEEE Journal Of Solid-State Circuits, pp. 185-186, June 1975
3. Mihaly Nemes, "Driving Large Capacitances in MOS LSI Systems", IEEE Journal Of Solid-State Circuits, Vol. SC-19, No.1, pp. 159-161, February 1984
4. N.C. Li, Gene L. Haviland, A.A. Tuszynski, "CMOS Tapered Buffer", IEEE Journal Of Solid-State Circuits, Vol. 25, No.4, pp. 1005- 1008, August 1990
5. Ivan E. Sutherland, Robert F. Sproull, "Logical Effort: Designing for Speed on the Back of an Envelope", Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI, 1991.
6. Joo-Sun Choi, Kwyro Lee, "Design of CMOS Tapered Buffer for Minimum Power-Delay Product", IEEE Journal Of Solid-State Circuits, Vol. 29, No.9, pp. 1142-1145, September 1994
7. Brian s. Cherkauer, Eby G. Friedman, "A Unified Design Methodology for CMOS Tapered Buffers", IEEE Transactions On Very-Large Scale Integration (VLSI) Systems, Vol. 3, No. 1, pp. 99-111, March 1995
8. Takayasu Sakurai, A. Richard Newton, "Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas", IEEE Journal Of Solid-State Circuits, Vol. 25, No.2, pp. 584-594, April 1990
9. Anthony J. Stratakos, Seth R. Sanders, Robert W. Brodersen, "A low-voltage CMOS DC-DC converter for a portable battery-operated system", IEEE Power Electronics Specialists Conference, Vol. 1, pp.619 - 626, June 1994
10. Volkan Kursun et al., "Low-Voltage-Swing Monolithic dc-dc Conversion", IEEE Transactions On Circuits And Systems, Vol. 51, No. 5, pp. 241-247, May 2004