A 2.5Gb/s Burst-Mode CDR based on a 1/8th rate Dual Pulse Ring Oscillator

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

Volumn , Issue , 2007, Pages 357-360

  Gierkink, Sander L J ^a  

^a Conexant Systems ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; LOCKS (FASTENERS);

DUAL-PULSES; INPUT BUFFERS; JITTER TOLERANCE; LOOP FILTER; OUTPUT BUFFER; PHASE-INDEPENDENT; PHASE-LOCKING; RING OSCILLATOR;

CLOCK AND DATA RECOVERY CIRCUITS (CDR CIRCUITS);

EID: 48849092316     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2007.4405752     Document Type: Conference Paper

References (4)

1. M. Banu, A. Dunlop, "A 660Mb/s CMOS Clock Recovery Circuit with Instantaneous Locking for NRZ Data and Burst-Mode Transmission", ISSCC Dig. Tech. Papers, pp 102-103, Feb. 1993.
2. M. Nogawa, et al. "A 10Gb/s Burst-Mode CDR IC in 0. 13m CMOS", ISSCC Dig. Tech. Papers, pp 228-229, Feb. 2005.
3. S. L. J. Gierkink, A. J. M. van Tuijl, "A Coupled Sawtooth Oscillator Combining Low Jitter With High Control Linearity", IEEE J. Solid-State Circuits, vol. 37, no. 6, pp. 702-710, Jun 2002.
4. S. Ye, L. Jansson, I. Galton, "A Multiple-Crystal Interface PLL With VCO Realignment to Reduce Phase Noise", IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1795-1803, Dec 2002.