Floorplan design for multi-million gate FPGAs

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2004, Pages 292-299

  Cheng, Lei ^a   Wong, Martin D F ^a  

^a University of Illinois at Urbana Champaign   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONFIGURABLE LOGIC BLOCKS (CLB); FLOORPLAN DESIGN; HETEROGENEOUS LOGIC RESOURCES;

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; MATHEMATICAL MODELS; PROBLEM SOLVING;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 16244395792     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2004.1382589     Document Type: Conference Paper

References (14)

1. Maogang Wang, Abhishek Ranjan, and Salil Raje. Multi-million gate FPGA physical design challenges. ICCAD, pages 891-898, 2003.
2. D. Gregory, K. Bartlet, A. De Geus, and G. Hachtel. Socrates: a system for automatically synthesizing and optimizing combinational logic. DAC, pages 79-85, 1996.
3. Robert Francis, Jonathan Rose, and Zvonko Vranesic. Chortle-erf: fast technology mapping for lookup table-based FPGAs. DAC, pages 227 - 233, 1991.
4. C. Sechen and K. Lee. An improved simulated annealing algorithm for row-based placement. ICCAD, pages 478-481, 1987.
5. J. Rose and S. Brown. Flexibility of interconnection structures in field-programmable gate arrays. IEEE Journal of Solid State Circuits, 26(3):277-282, March 1991.
6. George Karypis, Rajat Aggarwal, Vipin Kumar, and Shashi Shekhar. Multilevel hypergraph partitioning: application in VLSI domain. DAC, pages 526 - 529, 1997.
7. Ralph H. J. M. Orten. Automatic floorplan design. DAC, pages 261-267, 1982.
8. H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani. Rectangle-packing-based module palcement. ICCAD, pages 472-479, 1995.
9. X. Hong et al. Corner Block List: an effective and efficient topological representation of non-slicing floorplan. ICCAD, pages 8-11, 2000.
10. E. F. Y. Yong, C. C. N. Chu, and Z. C. Shen. Twin Binary Sequences: a nonredundant representation for general nonslicing floorplan. TCAD, 22(4):457-469, April 2003.
11. J. M. Emmert and D. Bhatia. A methodology for fast FPGA floorplanning. International Symposium on Field Programmable Gate Arrays, 1999.
12. http://www.xilinx.com.
13. Larry J. Stockmeyer. Optimal orientations of cells in slicing floorplan designs. Information and Control, 57(2/3):91-101, 1983.
14. D. F. Wong and C. L. Liu. A new algorithm for floorplan design. DAC, pages 101-107, 1986.