-
2
-
-
0011493977
-
A first generation DPGA implementation
-
E. Tau, D. Chen, I. Eslick, J. Brown, and A. DeHon, "A first generation DPGA implementation," in Canadian Workshop on Field-Programmable Devices (FPD), 1995, pp. 138-143.
-
(1995)
Canadian Workshop on Field-programmable Devices (FPD)
, pp. 138-143
-
-
Tau, E.1
Chen, D.2
Eslick, I.3
Brown, J.4
DeHon, A.5
-
3
-
-
0031346317
-
A time-multiplexed FPGA
-
S. Trimberger, D. Carberry, A. Johnson, and J. Wong, "A time-multiplexed FPGA," in Proc. 5th IEEE Symp. on Field-Programmable Custom Computing Machines (FCCM), 1997, pp. 22-28.
-
(1997)
Proc. 5th IEEE Symp. on Field-programmable Custom Computing Machines (FCCM)
, pp. 22-28
-
-
Trimberger, S.1
Carberry, D.2
Johnson, A.3
Wong, J.4
-
7
-
-
0032674941
-
Partitioning sequential circuits on dynamically reconfigurable FPGAs
-
June
-
D. Chang and M. Marek-Sadowska, "Partitioning sequential circuits on dynamically reconfigurable FPGAs," IEEE Trans. on Computers, vol. 48, no. 6, pp. 565-578, June 1999.
-
(1999)
IEEE Trans. on Computers
, vol.48
, Issue.6
, pp. 565-578
-
-
Chang, D.1
Marek-Sadowska, M.2
-
8
-
-
0036374232
-
Temporal logic replication for dynamically reconfigurable FPGA partitioning
-
ACM, Apr.
-
W.-K. Mak and E. F. Young, "Temporal logic replication for dynamically reconfigurable FPGA partitioning," in Proc. ACM Int. Symp. on Physical Design (ISPD). ACM, Apr. 2002, pp. 190-195.
-
(2002)
Proc. ACM Int. Symp. on Physical Design (ISPD)
, pp. 190-195
-
-
Mak, W.-K.1
Young, E.F.2
-
10
-
-
0035472753
-
Generic ILP-based approaches for time-multiplexed FPGA partitioning
-
Oct.
-
G.-M. Wu, J.-M. Lin, and Y.-W. Chang, "Generic ILP-based approaches for time-multiplexed FPGA partitioning," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 10, pp. 1266-1274, Oct. 2001.
-
(2001)
IEEE Trans. on Computer-aided Design of Integrated Circuits and Systems
, vol.20
, Issue.10
, pp. 1266-1274
-
-
Wu, G.-M.1
Lin, J.-M.2
Chang, Y.-W.3
-
11
-
-
0032686439
-
Temporal partitioning and scheduling data flow graphs for reconfigurable computers
-
June
-
K. M. G. Puma and D. Bhatia, "Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers," IEEE Trans. on Computers, vol. 48, no. 6, pp. 579-590, June 1999.
-
(1999)
IEEE Trans. on Computers
, vol.48
, Issue.6
, pp. 579-590
-
-
Puma, K.M.G.1
Bhatia, D.2
-
13
-
-
84893633166
-
An effective design system for dynamically reconfigurable architectures
-
IEEE Computer Society
-
S. Govindarajan, I. Ouaiss, M. Kaul, V. Srinivasan, and R. Vemuri, "An Effective Design System for Dynamically Reconfigurable Architectures," in Proc. 6th IEEE Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE Computer Society, 1998, pp. 312-313.
-
(1998)
Proc. 6th IEEE Symp. on Field-programmable Custom Computing Machines (FCCM)
, pp. 312-313
-
-
Govindarajan, S.1
Ouaiss, I.2
Kaul, M.3
Srinivasan, V.4
Vemuri, R.5
-
14
-
-
34548744135
-
Optimal temporal partitioning and synthesis for reconfigurable architectures
-
IEEE Computer Society
-
M. Kaul and R. Vemuri, "Optimal Temporal Partitioning and Synthesis for Reconfigurable Architectures," in Proc. Design, Automation and Test in Europe Conf. (DATE). IEEE Computer Society, 1998, pp. 389-396.
-
(1998)
Proc. Design, Automation and Test in Europe Conf. (DATE)
, pp. 389-396
-
-
Kaul, M.1
Vemuri, R.2
-
16
-
-
0035242911
-
Fine-grained and coarse-grained behavioral partitioning with effective utilization of memory and design space exploration for multi-FPGA architectures
-
Feb.
-
V. Srinivasan, S. Govindarajan, and R. Vemuri, "Fine-Grained and Coarse-Grained Behavioral Partitioning With Effective Utilization of Memory and Design Space Exploration for Multi-FPGA Architectures," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 9, no. 1, pp. 140-158, Feb. 2001.
-
(2001)
IEEE Trans. on Very Large Scale Integration (VLSI) Systems
, vol.9
, Issue.1
, pp. 140-158
-
-
Srinivasan, V.1
Govindarajan, S.2
Vemuri, R.3
-
17
-
-
0347117076
-
Optimal FPGA module placement with temporal precedence constraints
-
IEEE Computer Society
-
S. Fekete, E. Köhler, and J. Teich, "Optimal FPGA Module Placement with Temporal Precedence Constraints," in Proc. Design, Automation and Test in Europe Conf. (DATE). IEEE Computer Society, 2001, pp. 658-665.
-
(2001)
Proc. Design, Automation and Test in Europe Conf. (DATE)
, pp. 658-665
-
-
Fekete, S.1
Köhler, E.2
Teich, J.3
-
18
-
-
0035338121
-
Optimization of dynamic hardware reconfigurations
-
May
-
J. Teich, S. Fekete, and J. Schepers, "Optimization of Dynamic Hardware Reconfigurations," Journal of Supercomputing, vol. 19, no. 1, pp. 57-75, May 2001.
-
(2001)
Journal of Supercomputing
, vol.19
, Issue.1
, pp. 57-75
-
-
Teich, J.1
Fekete, S.2
Schepers, J.3
-
19
-
-
84956862038
-
Hardware-software codesign for dynamically reconfigurable architectures
-
Springer
-
K. Chatka and R. Vemuri, "Hardware-Software Codesign for Dynamically Reconfigurable Architectures," in Field-Programmable Logic and Applications (Proc. FPL). Springer, 1999, pp. 175-184.
-
(1999)
Field-programmable Logic and Applications (Proc. FPL)
, pp. 175-184
-
-
Chatka, K.1
Vemuri, R.2
-
20
-
-
0034174174
-
The garp architecture and C compiler
-
Apr.
-
T. J. Callahan, J. R. Hauser, and J. Wawrzynek, "The Garp architecture and C compiler," IEEE Computer, vol. 33, no. 4, pp. 62-69, Apr. 2000.
-
(2000)
IEEE Computer
, vol.33
, Issue.4
, pp. 62-69
-
-
Callahan, T.J.1
Hauser, J.R.2
Wawrzynek, J.3
-
22
-
-
79955142752
-
XPP-VC: A c compiler with temporal partitioning for the PACT-XPP architecture
-
LNCS 2438, Springer Verlag
-
J. M. Cardoso and M. Weinhardt, "XPP-VC: a c compiler with temporal partitioning for the PACT-XPP architecture," in Field-Programmable Logic and Applications (Proc. FPL), ser. LNCS, vol. 2438. LNCS 2438, Springer Verlag, 2002, pp. 864-874.
-
(2002)
Field-programmable Logic and Applications (Proc. FPL), Ser. LNCS
, vol.2438
, pp. 864-874
-
-
Cardoso, J.M.1
Weinhardt, M.2
-
24
-
-
0034174187
-
PipeRench: A reconfigurable architecture and compiler
-
Apr.
-
S. C. Goldstein, H. Schmit, M. Budiu, S. Cadambi, M. Moe, and R. R. Taylor, "PipeRench: A reconfigurable architecture and compiler," IEEE Computer, vol. 33, no. 4, pp. 70-77, Apr. 2000.
-
(2000)
IEEE Computer
, vol.33
, Issue.4
, pp. 70-77
-
-
Goldstein, S.C.1
Schmit, H.2
Budiu, M.3
Cadambi, S.4
Moe, M.5
Taylor, R.R.6
-
25
-
-
0036045954
-
PipeRech: A virtualized programmable datapath in 0.18 micron technology
-
H. Schmit, D. Whelihan, M. Moe, B. Levine, and R. R. Taylor, "PipeRech: A virtualized programmable datapath in 0.18 micron technology," in Proc. 24th IEEE Custom Integrated Circuits Conf. (CICC), 2002, pp. 63-66.
-
(2002)
Proc. 24th IEEE Custom Integrated Circuits Conf. (CICC)
, pp. 63-66
-
-
Schmit, H.1
Whelihan, D.2
Moe, M.3
Levine, B.4
Taylor, R.R.5
-
26
-
-
84947574774
-
Stream computations organized for reconfigurable execution (SCORE)
-
LNCS 1896, Springer-Verlag
-
E. Caspi, M. Chu, R. Huang, J. Yeh, J. Wawrzynek, and A. DeHon, "Stream computations organized for reconfigurable execution (SCORE)," in Field-Programmable Logic and Applications (Proc. FPL). LNCS 1896, Springer-Verlag, 2000, pp. 605-614.
-
(2000)
Field-programmable Logic and Applications (Proc. FPL)
, pp. 605-614
-
-
Caspi, E.1
Chu, M.2
Huang, R.3
Yeh, J.4
Wawrzynek, J.5
DeHon, A.6
-
27
-
-
0029370810
-
WASMII: An MPLD with data-driven control on a virtual hardware
-
Xiaoping Ling and H. Amano, "WASMII: An MPLD with data-driven control on a virtual hardware," The Journal of Supercomputing, vol. 9, no. 3, pp. 253-276, 1995.
-
(1995)
The Journal of Supercomputing
, vol.9
, Issue.3
, pp. 253-276
-
-
Ling, X.1
Amano, H.2
-
28
-
-
85027148415
-
2-II
-
Springer, June
-
2-II," in Proc. 2nd Parallel Architectures and Languages, Europe, ser. LNCS 365. Springer, June 1989, pp. 118-135.
-
(1989)
Proc. 2nd Parallel Architectures and Languages, Europe, Ser. LNCS
, vol.365
, pp. 118-135
-
-
Ling, X.-P.1
Amano, H.2
-
31
-
-
84920348239
-
Multitasking on FPGA coprocessors
-
Springer
-
H. Simmler, L. Levinson, and R. Männer, "Multitasking on FPGA Coprocessors," in Proceedings of the 10th International Workshop on Field Programmable Gate Arrays (FPL). Springer, 2000, pp. 121-130.
-
(2000)
Proceedings of the 10th International Workshop on Field Programmable Gate Arrays (FPL)
, pp. 121-130
-
-
Simmler, H.1
Levinson, L.2
Männer, R.3
-
33
-
-
84893789292
-
Online scheduling for block-partitioned reconfigurable devices
-
IEEE Computer Society, March
-
H. Walder and M. Platzner, "Online Scheduling for Block-partitioned Reconfigurable Devices," in Proceedings of the International Conference on Design, Automation and Test in Europe (DATE). IEEE Computer Society, March 2003, pp. 290-295.
-
(2003)
Proceedings of the International Conference on Design, Automation and Test in Europe (DATE)
, pp. 290-295
-
-
Walder, H.1
Platzner, M.2
-
34
-
-
0347566174
-
Online scheduling and placement of real-time tasks to partially reconfigurable devices
-
IEEE Computer Society, December
-
C. Steiger, H. Walder, M. Platzner, and L. Thiele, "Online Scheduling and Placement of Real-time Tasks to Partially Reconfigurable Devices," in Proceedings of the 24th International Real-Time Systems Symposium (RTSS). IEEE Computer Society, December 2003, pp. 224-235.
-
(2003)
Proceedings of the 24th International Real-time Systems Symposium (RTSS)
, pp. 224-235
-
-
Steiger, C.1
Walder, H.2
Platzner, M.3
Thiele, L.4
-
37
-
-
0033690040
-
A hardware virtual machine for the networked reconfiguration
-
Y. Ha, P. Schaurnont, M. Engels, S. Vernalde, F. Potargent, L. Rijnders, and H. D. Man, "A hardware virtual machine for the networked reconfiguration," in IEEE International Workshop on Rapid System Prototyping, 2000, pp. 194-199.
-
(2000)
IEEE International Workshop on Rapid System Prototyping
, pp. 194-199
-
-
Ha, Y.1
Schaurnont, P.2
Engels, M.3
Vernalde, S.4
Potargent, F.5
Rijnders, L.6
Man, H.D.7
-
39
-
-
0036469962
-
Building a virtual framework for networked reconfigurable hardware and software objects
-
February
-
Y. Ha, S. Vernalde, P. Schaumont, M. Engels, R. Lauwereins, and H. De Man, "Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects," Journal of Supercomputing, vol. 21, no. 2, pp. 131-144, February 2002.
-
(2002)
Journal of Supercomputing
, vol.21
, Issue.2
, pp. 131-144
-
-
Ha, Y.1
Vernalde, S.2
Schaumont, P.3
Engels, M.4
Lauwereins, R.5
De Man, H.6
|