Review on process-induced strain techniques for advanced logic technologies

15th IEEE International Conference on Advanced Thermal Processing of Semiconductors, RTP 2007

Volumn , Issue , 2007, Pages 19-29

  Wiatr, M ^a   Feudel, Th ^a   Wei, A ^a   Mowry, A ^a   Boschke, R ^a   Javorka, P ^a   Gehring, A ^a   Kammler, T ^a   Lenski, M ^a   Frohberg, K ^a   Richter, R ^a   Horstmann, M ^a   Greenlaw, D ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CRYSTALS; ELECTRIC CONDUCTIVITY; INTERNET PROTOCOLS; NANOTECHNOLOGY; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR MATERIALS; SILICON CARBIDE;

45NM NODES; CHANNEL MOBILITIES; CMOS FLOWS; FLASH ANNEALS; INDUCED STRAINS; LOGIC TECHNOLOGIES; OVERLAYERS; PERFORMANCE IMPROVEMENTS; PROXIMITY EFFECTS; SHORT CHANNELS; SOI SUBSTRATES; SPACER MATERIALS; TECHNOLOGY NODES;

RAPID THERMAL ANNEALING;

EID: 47949091640     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RTP.2007.4383814     Document Type: Conference Paper

References (14)

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