Integration challenges for advanced process-strained CMOS on biaxially-strained SOI (SSOI) substrates

ECS Transactions

Volumn 6, Issue 1, 2007, Pages 15-22

  Wei, A ^a   Dunkel S ^a   Boschke, R ^a   Kammler, T ^a   Hempel, K ^a   Rinderknecht, J ^a   Horstmann, M ^a   Cayrefourcq, I ^b   Metral, F ^b   Kennard, M ^b   Guiot, E ^b  

^a IBM MICROELECTRONICS   (United States)

^b PARC TECHNOLOGIQUE DES FONTAINES   (France)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC GATES;

ADVANCED PROCESS; DRIVE CURRENTS; MULTIPLE STRESS; PROCESS INDUCED STRAINS; SHORT CHANNELS; SOURCE/DRAIN REGIONS; STRAINED-SOI; STRESS MEMORIZATION TECHNIQUES;

CMOS INTEGRATED CIRCUITS;

EID: 45849086584     PISSN: 19385862     EISSN: 19386737     Source Type: Conference Proceeding    
DOI: 10.1149/1.2727383     Document Type: Conference Paper

References (12)

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