Recovery requirements of branch prediction storage structures in the presence of mispredicted-path execution

International Journal of Parallel Programming

Volumn 25, Issue 5, 1997, Pages 363-383

  Jourdan, Stephan ^a   Stark, Jared ^a   Hsing, Tse Hao ^a   Patt, Yale N ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Architecture; Branch prediction; Processor design; Speculative execution; Superscalar

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SYSTEM RECOVERY; DESIGN; PROGRAM PROCESSORS;

BRANCH HISTORY REGISTER; BRANCH PREDICTION; BRANCH TARGET BUFFER; PATTERN HISTORY TABLES; RETURN ADDRESS STACK; SPECULATIVE EXECUTION; SUPERSCALAR;

PARALLEL PROCESSING SYSTEMS;

EID: 33845269010     PISSN: 08857458     EISSN: None     Source Type: Journal    
DOI: 10.1007/BF02699883     Document Type: Article

References (21)

1. M. G. Butler, Aggressive Execution Engines for Surpassing Single Basic Block Execution, Ph.D. Thesis, University of Michigan, 1993.
2. J. Pierce and T. Mudge, The Effect of Speculative Execution on Cache Performance, Proc. Int'l Parallel Processing Symp. (April 1994).
3. J. Pierce and T. Mudge, Wrong-Path Instruction Prefetching, Proc. 29th Ann. ACM/IEEE Int'l Symp. Microarchitecture (December 1996).
4. M. G. Butler and Y. N. Patt, An Investigation of the Performance of Various Dynamic Scheduling Techniques, Proc. 25th Ann. ACM/IEEE Int'l Symp. Microarchitecture, (December 1992).
5. T. Yeh and Y. N. Patt, Alternative Implementations of Two-Level Adaptive Branch Prediction, Proc. I9lh Ann. Symp. on Computer Architecture (May 1992).
6. T. Yeh, Two-Level Adaptive Branch Prediction and Instruction Fetch Mechanisms for High Performance Superscalar Processors, Ph.D. Thesis, University of Michigan (1993).
7. M. Johnson, Superscalar Microprocessor Design, Prentice-Hall (1991).
8. A. R. Talcott, W. Yamamoto, M. J. Serrano, R. C. Wood, and M. Nemirovsky, The Impact of Unresolved Branches on Branch Prediction Scheme Performance, Proc. 21st Ann. Int'l Symp. Computer Architecture (April 1994).
9. E. Hao, P-Y Chang, and Y. N. Patt, The effect of Speculatively Updating Branch History on Branch Prediction Accuracy, Revisited, Proc. 27th Ann. Int'l Symp. Microarchitecture (November 1994).
10. Y. N. Patt, W. Hwu, and M. Shebanow, HPS, A New Microarchitecture: Rationale and Introduction, Proc. 18th Ann. Workshop on Microprogramming (December 1985).
11. L. Gwennap, Intel's P6 Uses Decoupled Superscalar Design, Microprocessor Report, Vol. 9 No. 2, 1995.
12. S. Ewedemi, D. Todd, and J. Yen, Design Issues of the High Performance PowerPC 620 Microprocessor, Somerset Design Center (December 1994).
13. L. Gwennap, Digital 21264 Sets New Standard, Microprocessor Report, Vol. 10, No. 14 (1996).
14. R. M. Tomasulo, An Efficient Algorithm for Exploiting Multiple Arithmetic Units, IBM J. Res. Develop., Vol. II (January 1967).
15. W. Hwu and Y. N. Patt, Checkpoint Repair for Out-of-Order Execution Machines, IEEE Trans. Comp. (December 1987).
16. M. G. Butler and Y. N. Patt, An Area-Efficient Register Alias Table For Implementing HPS, Proc. Int'l Conf. Parallel Processing (1990).
17. S. McFarling, Combining Branch Predictors, Technical Report TN-36, Digital Western Research Laboratory (June 1993).
18. J. E. Smith and A. R. Pleszkun, Implementation of Precise Interrupts in Pipelined Processors, Proc. 12th Ann. Int'l Symp. Computer Architecture (June 1989).
19. M. G. Butler and Y. N. Patt, A Comparative Performance Evaluation of Various State Maintenance Mechanisms, Proc. 26th Ann. ACM I IEEE Int'l Symp. Microarchitecture (December 1993).
20. S. Jourdan, P. Sainrat, and D. Litaize, Exploring Configurations of Functional Units in an Out-of-Order Superscalar Processor, Proc. 22nd Ann. Symp. Computer Architecture (June 1995).
21. S. Simone, A. Essen, A. Ike, A. Krishnamoorthy, N. Patker, M. Ramaswami, and V. Thirumalaiswamy, Implementation Trade-offs in Using a Restricted Data Flow Architecture in a High Performance RISC Microprocessor, Proc. 22nd Ann. Int'l Symp. Computer Architecture (June 1995).