Long length LDPC code construction and the corresponding decoder implementation with adjustable parallelism

IEEE Vehicular Technology Conference

Volumn , Issue , 2008, Pages 1423-1427

  Lin, Chia Yu ^a   Ku, Mong Kai ^a   Chien, Yi Hsing ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Low density parity check code; Partially parallel decoder; Progressive edge growth (PEG); Quasi cyclic (QC) codes

Indexed keywords

CHANNEL CODING; COMMUNICATION CHANNELS (INFORMATION THEORY); DECODING; FLOORS; GROWTH (MATERIALS); IMAGE COMPRESSION; ITERATIVE DECODING; POLYETHYLENE GLYCOLS; QUANTUM THEORY; SIGNAL ENCODING; TRANSCEIVERS; TURBO CODES;

BLOCK LENGTHS; CODE CONSTRUCTIONS; CODE LENGTHS; CODING GAINS; CODING PERFORMANCE; DECODER ARCHITECTURES; DECODER IMPLEMENTATIONS; ERROR FLOORS; GROWTH ALGORITHMS; LDPC CODES; LOW-DENSITY PARITY-CHECK CODE; PARITY CHECK MATRICES; PARTIALLY-PARALLEL DECODER; PROGRESSIVE EDGE-GROWTH (PEG); QUASI-CYCLIC; QUASI-CYCLIC (QC) CODES; SECOND LEVELS; SUB-MATRICES; THROUGHPUT PERFORMANCE;

CODES (SYMBOLS);

EID: 47749094712     PISSN: 15502252     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VETECS.2008.299     Document Type: Conference Paper

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