L2 cache modeling for scientific applications on chip multi-processors

Proceedings of the International Conference on Parallel Processing

Volumn , Issue , 2007, Pages 51-

  Song, Fengguang ^a   Moore, Shirley ^a   Dongarra, Jack ^a,b  

^a University of Tennessee   (United States)

^b OAK RIDGE NATIONAL LABORATORY   (United States)

Author keywords

Architecture; Cache performance modeling; Chip multi processor; Multi threaded programming

Indexed keywords

ARCHITECTURE; CACHE MEMORY; DATA SHARING; FORECASTING; PARALLEL PROCESSING SYSTEMS;

AVERAGE RELATIVE ERROR; CACHE PERFORMANCE; CHIP MULTI-PROCESSORS; CYCLE-ACCURATE SIMULATORS; MULTITHREADED; PERFORMANCE DEGRADATION; SCIENTIFIC APPLICATIONS; SPARSE MATRIX VECTOR PRODUCTS;

MATRIX ALGEBRA;

EID: 47249151449     PISSN: 01903918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICPP.2007.52     Document Type: Conference Paper

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