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Journal of VLSI Signal Processing

Volumn 9, Issue 3, 1995, Pages 181-191

Parallel reduced area multipliers

(3) Bickerstaff, K'Andrea C a Schulte, Michael J b Swartzlander Jr , Earl E b

a INTEL CORPORATION (United States)

b UNIVERSITY OF TEXAS AT AUSTIN (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; COMPUTER AIDED DESIGN; ESTIMATION; LOGIC GATES; MATRIX ALGEBRA; NUMERICAL ANALYSIS; SEQUENTIAL CIRCUITS; VLSI CIRCUITS;

BRAUN CARRY SAVE SCHEME; FAST CARRY PROPAGATE ADDER; PARALLEL REDUCED AREA MULTIPLIERS; PIPELINED MULTIPLIERS;

MULTIPLYING CIRCUITS;

EID: 0029287997 PISSN: 09225773 EISSN: 1573109X Source Type: Journal
DOI: 10.1007/BF02407084 Document Type: Article

Times cited : (44)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.