Combinational equivalence checking using incremental SAT solving, output ordering, and resets

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2007, Pages 938-943

  Disch, Stefan ^a   Scholl, Christoph ^a  

^a UNIVERSITY OF FREIBURG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; EQUIVALENCE CLASSES; INDUSTRIAL ENGINEERING; INTEGRATED CIRCUIT MANUFACTURE; MECHANIZATION; MODEL CHECKING;

BOUNDED MODEL CHECKING (BMC); CIRCUIT DESIGNS; CIRCUIT STRUCTURES; COMBINATIONAL EQUIVALENCE CHECKING; DESIGN AUTOMATION CONFERENCE (DAC); EQUIVALENCE CHECKING; EXPERIMENTAL RESULTS; NOVEL METHODS; SAT SOLVING; SOUTH PACIFIC; TRADITIONAL METHODS;

ELECTRIC NETWORK ANALYSIS;

EID: 46649112518     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2007.358110     Document Type: Conference Paper

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