CirCUs: A satisfiability solver geared towards bounded model checking

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 3114, Issue , 2004, Pages 519-522

  Jin, HoonSang ^a   Awedh, Mohammad ^a   Somenzi, Fabio ^a  

^a UNIVERSITY OF COLORADO   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED ANALYSIS; FORMAL LOGIC;

BOOLEAN CIRCUIT; BOUNDED MODEL CHECKING; DECISION HEURISTICS; EARLY TERMINATION; SAT-SOLVING; SATISFIABILITY SOLVERS;

MODEL CHECKING;

EID: 35048848122     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-27813-9_50     Document Type: Article

References (19)

1. M. Awedh and F. Somenzi. Proving more properties with bounded model checking. These proceedings.
2. A. Biere, A. Cimatti, E. Clarke, and Y. Zhu. Symbolic model checking without BDDs. In Fifth International Conference on Tools and Algorithms for Construction and Analysis of Systems (TACAS'99), pages 193-207, Amsterdam, The Netherlands, Mar. 1999. LNCS 1579.
3. R. K. Brayton et al. VIS: A system for verification and synthesis. In T. Henzinger and R. Alur, editors, Eighth Conference on Computer Aided Verification (CAV'96), pages 428-432. Springer-Verlag, Rutgers University, 1996. LNCS 1102.
4. G. Cabodi, S. Nocco, and S. Quer. Improving SAT-based bounded model checking by means of BDD-based approximate traversal. In Proceedings of the Conference on Design, Automation and Test in Europe, pages 898-905, Munich, Germany, Mar. 2003.
5. N. Eén and N. Sörensson. Temporal induction by incremental SAT solving. Electronic Notes in Theoretical Computer Science, 89(4), 2003. First International Workshop on Bounded Model Checking. http://www.elsevier.nl/locate/entcs/.
6. E. Goldberg and Y. Novikov. BerkMin: A fast and robust SAT-solver. In Proceedings of the Conference on Design, Automation and Test in Europe, pages 142-149, Paris, France, Mar. 2002.
7. H. Jin and F. Somenzi. CirCUs: Speeding up circuit SAT with BDD-based implications. Submitted for publication, Apr. 2004.
8. A. Kuehlmann, M. K. Ganai, and V. Paruthi. Circuit-based Boolean reasoning. In Proceedings of the Design Automation Conference, pages 232-237, Las Vegas, NV, June 2001.
9. K. L. McMillan. Applying SAT methods in unbounded symbolic model checking. In E. Brinksma and K. G. Larsen, editors, Fourteenth Conference on Computer Aided Verification (CAV'02), pages 250-264. Springer-Verlag, Berlin, July 2002. LNCS 2404.
10. K. L. McMillan. Interpolation and SAT-based model checking. In W. A. Hunt, Jr. and F. Somenzi, editors, Fifteenth Conference on Computer Aided Verification (CAV'03), pages 1-13. Springer-Verlag, Berlin, July 2003. LNCS 2725.
11. M. Moskewicz, C. F. Madigan, Y. Zhao, L. Zhang, and S. Malik. Chaff: Engineering an efficient SAT solver. In Proceedings of the Design Automation Conference, pages 530-535, Las Vegas, NV, June 2001.
12. K. Ravi and F. Somenzi. Minimal assignments for bounded model checking. In International Conference on Tools and Algorithms for Construction and Analysis of Systems (TACAS'04), pages 31-45, Barcelona, Spain, Apr. 2004. LNCS 2988.
13. M. Sheeran, S. Singh, and G. Stålmarck. Checking safety properties using induction and a SAT-solver. In W. A. Hunt, Jr. and S. D. Johnson, editors, Formal Methods in Computer Aided Design, pages 108-125. Springer-Verlag, Nov. 2000. LNCS 1954.
14. O. Shtrichman. Pruning techniques for the SAT-based bounded model checking problem. In Correct Hardware Design and Verification Methods (CHARME 2001), pages 58-70, Livingston, Scotland, Sept. 2001. Springer. LNCS 2144.
15. J. P. M. Silva and K. A. Sakallah. Grasp - a new search algorithm for satisfiability. In Proceedings of the International Conference on Computer-Aided Design, pages 220-227, San Jose, CA, Nov. 1996.
16. URL: http://vlsi.colorado.edu/∼vis.
17. J. Whittemore, J. Kim, and K. Sakallah. SATIRE: A new incremental satisfiability engine. In Proceedings of the Design Automation Conference, pages 542-545, Las Vegas, NV, June 2001.
18. H. Zhang. SATO: An efficient propositional prover. In Proceedings of the International Conference on Automated Deduction, pages 272-275, July 1997. LNAI 1249.
19. L. Zhang and S. Malik. Validating SAT solvers using an independent resolution-based checker: Practical implementations and other applications. In Design, Automation and Test in Europe (DATE'03), pages 880-885, Munich, Germany, Mar. 2003.