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Volumn , Issue , 2005, Pages 154-159

Total leakage power optimization with improved mixed gates

Author keywords

Leakage currents; MVT; Threshold voltage

Indexed keywords

LEAKAGE CURRENTS; SYSTEMS ANALYSIS;

EID: 46449097844     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SBCCI.2005.4286849     Document Type: Conference Paper
Times cited : (10)

References (15)
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    • Borkar, Y.S. VLSI Design Challenges for Gigascale Integration, keynote address at 18th Conference on VLSI Design, Kolkata, India, 2005.
    • Borkar, Y.S. VLSI Design Challenges for Gigascale Integration, keynote address at 18th Conference on VLSI Design, Kolkata, India, 2005.
  • 3
    • 46449090668 scopus 로고    scopus 로고
    • BSIM Research Group Berkeley short channel IGFET model version 4, available at hrtp://www-device.eecs.berkeley.edu/~bsim3/9.html, 2004.
    • BSIM Research Group Berkeley short channel IGFET model version 4", available at hrtp://www-device.eecs.berkeley.edu/~bsim3/9.html, 2004.
  • 4
    • 14244267091 scopus 로고    scopus 로고
    • Device Group at UC Berkeley, available at, 2002
    • Device Group at UC Berkeley Berkeley Predictive Technology Models, available at http://www-device.eecs.berkeley.edu/~ptm, 2002.
    • Berkeley Predictive Technology Models
  • 6
    • 0030697754 scopus 로고    scopus 로고
    • Transistor sizing issues and tool for multi-threshold CMOS technology
    • ISBN:0-89791-920-3, Anaheim, California, United States
    • Kao, J., Chandrakasan, A., and Antoniadis, D. Transistor sizing issues and tool for multi-threshold CMOS technology, In Proceedings of 34th Conference on Design Automation (DAC), pp. 409-414, ISBN:0-89791-920-3, Anaheim, California, United States, 1997.
    • (1997) Proceedings of 34th Conference on Design Automation (DAC) , pp. 409-414
    • Kao, J.1    Chandrakasan, A.2    Antoniadis, D.3
  • 9
    • 1542329235 scopus 로고    scopus 로고
    • Modelling and Estimation of Total Leakage Current in Nano-sclaed CMOS Devices Considering the Effect of Parameter Variation
    • Seoul, Korea
    • Mukhopadhyay, S. and Roy, K. Modelling and Estimation of Total Leakage Current in Nano-sclaed CMOS Devices Considering the Effect of Parameter Variation, In Proceedings of ISLPED'03, Seoul, Korea, 2003.
    • (2003) Proceedings of ISLPED'03
    • Mukhopadhyay, S.1    Roy, K.2
  • 11
    • 27944448040 scopus 로고    scopus 로고
    • Sill, F., Grassert F., Timmermann, D. Reducing Leakage with Mixed-Vth (MVT), In Proceedings of 18th Conference on VLSI Design, S. 874-877, ISBN: 0-7695-2264-5, Kolkata, Indien, January 2005.
    • Sill, F., Grassert F., Timmermann, D. Reducing Leakage with Mixed-Vth (MVT), In Proceedings of 18th Conference on VLSI Design, S. 874-877, ISBN: 0-7695-2264-5, Kolkata, Indien, January 2005.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.