Low power gate-level design with mixed-Vth (MVT) techniques

Proceedings - 17th Symposium on Integrated Cicuits and Systems Design, SBCCI2004

Volumn , Issue , 2004, Pages 278-282

  Sill, Frank ^a   Grassert, Frank ^a   Timmermann, Dirk ^a  

^a UNIVERSITY OF ROSTOCK   (Germany)

Author keywords

Leakage currents; MVT; Threshold voltage

Indexed keywords

ALGORITHMS; APPROXIMATION THEORY; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; GATES (TRANSISTOR); LOGIC DESIGN; MATHEMATICAL MODELS; OPTIMIZATION; THRESHOLD VOLTAGE;

HIGH-THRESHOLD VOLTAGE (HVT); LOW-THRESHOLD VOLTAGE TRANSISTORS (LVT); MIXED-VTH (MVT); SUBTHRESHOLD;

LEAKAGE CURRENTS;

EID: 14244249459     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1016568.1016641     Document Type: Conference Paper

References (17)

1. [Kim03] N.S. Kim, T. Austin, D. Blaauw, T. Mudge, K. Flautner, J.S. Hu, M.J. Irwin, M. Kandemir, and V. Narayanan, Leakage Current: Moore's Law Meets Static Power, in IEEE Computer, p. 68, no. 12 (2003).
2. [Kao00] J.K. Kao and A. Chandrakasan, Dual-Threshold Voltage Techniques for Low-Power Digital Circuits, in IEEE Journal of Solid State Circuits, p. 1009, no. 35 (2000).
3. [Han99] M. Hansen, H. Yalcin, and J. P. Hayes, Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering, in IEEE Design and Test, p. 72, no. 16 (1999).
4. [Sak90] T. Sakurai and A. Newton, Alpha-Power Law MOSFET Model and its Application to CMOS Inverter Delay and other Formulas, in IEEE Journal of Solid-State Circuits, pp. 584-594, no. 2 (1990).
5. [Sir04] N. Sirisantana and K. Roy, Low-Power Design Using Multiple Channel Lengths and Oxide Thicknesses, in IEEE Design and Test of computers, pp. 56-63, no. 1 (2004).
6. [Wei99] L.Wei, Z. Chen, K. Roy, M. Johnson, Y. Ye, and V.K. De, Design and Optimization of Dual-Threshold Circuits for Low-Voltage Low-Power Applications, in IEEE Trans, on VLSI Systems, pp.16, no. 1 (1999).
7. [Che0l] W.Chen, W.Hang, P.Kudva, G.D. Gristede, S.Kosonocky and R.V.Joshi, Mixed Multi-Threshold Differential Cascade Voltage Switch (MT-DCVS) Circuit Styles and Strategies for Low Power VLSI Design, ISLPED'0l, California, USA (2001).
8. th conference on Design automation, New Orleans, Louisiana (2002).
9. [Sun99] V.Sundararajan and K.Parhi, Low Power Synthesis of Dual Threshold Voltage CMOS VLSI Circuits, in Proceedings of the IEEE International Symposium on Low Power Electronics and Design, pp. 139-144 (1999).
10. th Design Automation Conference, pp. 430-435 (1999).
11. th Int. Conference on VLSI Design, pp. 24-29 (2000).
12. [Wei000b] L.Wei, K. Roy, and C. Koh, Power Minimization by Simultanous Dual-Vth Assignment and Gate-sizing, in Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 413-416 (2000).
13. [Ani03] M. Anis and M. Elmasry, in Multi-Threshold CMOS Digital Circuits, Kluwer Academic Publishers (2003).
14. [Vee00] H. Veendrick, in Deep-Submicron CMOS ICs, Kluwer Academic Publishers (2000).
15. [BPTM] Berkeley Predictive Technology Model, www-device.eecs.berkeley. edu/~ptm (2002).
16. [UMC] United Microelectronics Cooperation, www.umc.com
17. [TSMC] Taiwan Semiconductor Manufacturing Company Ltd., www.tsmc.com