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Volumn , Issue , 2005, Pages 874-877

Reducing leakage with mixed- Vth (MVT)

Author keywords

[No Author keywords available]

Indexed keywords

LEAKAGE REDUCTION;

EID: 27944448040     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICVD.2005.147     Document Type: Conference Paper
Times cited : (7)

References (11)
  • 1
    • 0346750535 scopus 로고    scopus 로고
    • Leakage current: Moore's law meets static power
    • N.S. Kim, et.al, Leakage Current: Moore's Law Meets Static Power, in IEEE Computer, p. 68, no. 12 (2003).
    • (2003) IEEE Computer , vol.12 , pp. 68
    • Kim, N.S.1
  • 4
    • 0034230287 scopus 로고    scopus 로고
    • Dual-threshold voltage techniques for low-power digital circuits
    • J.K. Kao and A. Chandrakasan, Dual-Threshold Voltage Techniques for Low-Power Digital Circuits, in IEEE Journal of Solid State Circuits, p. 1009, no. 35 (2000).
    • (2000) IEEE Journal of Solid State Circuits , vol.35 , pp. 1009
    • Kao, J.K.1    Chandrakasan, A.2
  • 6
    • 0033359507 scopus 로고    scopus 로고
    • Low power synthesis of dual threshold voltage CMOS VLSI circuits
    • V.Sundararajan and K.Parhi, Low Power Synthesis of Dual Threshold Voltage CMOS VLSI Circuits, in Proceedings of the IEEE ISLPED, pp. 139-144 (1999).
    • (1999) Proceedings of the IEEE ISLPED , pp. 139-144
    • Sundararajan, V.1    Parhi, K.2
  • 8
    • 0025415048 scopus 로고
    • Alpha-power law MOS-FET model and its application to CMOS inverter delay and other formulas
    • T. Sakurai and A. Newton, Alpha-Power Law MOS-FET Model and its Application to CMOS Inverter Delay and other Formulas, in IEEE Journal of Solid-State Circuits, pp. 584-594, no. 2 (1990).
    • (1990) IEEE Journal of Solid-state Circuits , vol.2 , pp. 584-594
    • Sakurai, T.1    Newton, A.2
  • 9
    • 14244249459 scopus 로고    scopus 로고
    • Low power gate-level design with Mixed-Vth (MVT) techniques
    • F. Sill, F.Grassert, D. Timmermann, Low Power Gate-level Design with Mixed-Vth (MVT) Techniques, SBCCI 2004.
    • SBCCI 2004
    • Sill, F.1    Grassert, F.2    Timmermann, D.3
  • 10
    • 27944484564 scopus 로고    scopus 로고
    • Berkeley Predictive Technology Model, www-device.eecs.berkeley.edu/~ptm (2002).
    • (2002)
  • 11
    • 0033359923 scopus 로고    scopus 로고
    • Unveiling the ISCAS-85 benchmarks: A case study in reverse engineering
    • M. Hansen, H. Yalcin, and J. P. Hayes, Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering, in IEEE Design and Test, p. 72, no. 16 (1999).
    • (1999) IEEE Design and Test , vol.16 , pp. 72
    • Hansen, M.1    Yalcin, H.2    Hayes, J.P.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.