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Volumn , Issue , 2006, Pages 252-261

Modelling and quantitative analysis of coupling mechanisms of programmable processor cores and arithmetic oriented eFPGA macros

Author keywords

[No Author keywords available]

Indexed keywords

CONSERVATION; DIGITAL ARITHMETIC; EFFICIENCY; ENERGY EFFICIENCY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); MECHANISMS; MODAL ANALYSIS; REDUCED INSTRUCTION SET COMPUTING; SEMICONDUCTOR DEVICE MANUFACTURE; TECHNOLOGY;

EID: 46449092178     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RECONF.2006.307777     Document Type: Conference Paper
Times cited : (11)

References (20)
  • 4
    • 22944443872 scopus 로고    scopus 로고
    • An Open Platform for Developing Multiprocessor SoCs
    • July
    • D. Nava, P. Blouet, P. Teninge, R. Wilson et. al., "An Open Platform for Developing Multiprocessor SoCs", IEEE Computer, Volume 38, Issue 7, July 2005
    • (2005) IEEE Computer , vol.38 , Issue.7
    • Nava, D.1    Blouet, P.2    Teninge, P.3    Wilson, R.4    et., al.5
  • 5
    • 34047191951 scopus 로고    scopus 로고
    • Application Specific Instruction Processor Based Implementation of a GNSS Receiver on an FPGA
    • March
    • G. Kappen, T.G. Noll, "Application Specific Instruction Processor Based Implementation of a GNSS Receiver on an FPGA", Proceedings IEEE DATE, March 2006
    • (2006) Proceedings IEEE DATE
    • Kappen, G.1    Noll, T.G.2
  • 7
    • 84990882958 scopus 로고    scopus 로고
    • Analysis of reconfigurable and heterogeneous architectures in the communication domain
    • St. Petersburg, June
    • H. Feldkämper, T. Gemmeke, H. Blume, T.G. Noll, "Analysis of reconfigurable and heterogeneous architectures in the communication domain", Proceedings of the IEEE ICCSC 2002, St. Petersburg, June 2002, pp. 190-193
    • (2002) Proceedings of the IEEE ICCSC 2002 , pp. 190-193
    • Feldkämper, H.1    Gemmeke, T.2    Blume, H.3    Noll, T.G.4
  • 10
    • 46449084145 scopus 로고    scopus 로고
    • National Institute of Standards and Technology
    • National Institute of Standards and Technology, FIPS PUB 46-3, 1999
    • (1999) , vol.46 -3
    • PUB, F.I.P.S.1
  • 11
    • 46449137048 scopus 로고    scopus 로고
    • OMAP platform
    • OMAP platform, http://focus.ti.com
  • 12
    • 28844462366 scopus 로고    scopus 로고
    • Architectural Trade-offs in Dynamically Reconfigurable Processors
    • Dissertation, Swiss Federal Institute of Technology, ETH Zürich
    • R. Enzler, "Architectural Trade-offs in Dynamically Reconfigurable Processors", Dissertation, Swiss Federal Institute of Technology, ETH Zürich, 2004
    • (2004)
    • Enzler, R.1
  • 13
    • 38249007189 scopus 로고
    • Design and implementation of an efficient general-purpose Median-Filter network
    • R. Gupta, P. Evripidou, "Design and implementation of an efficient general-purpose Median-Filter network", Digital Signal Processing, Vol. 3, 1993, pp. 64-72
    • (1993) Digital Signal Processing , vol.3 , pp. 64-72
    • Gupta, R.1    Evripidou, P.2
  • 15
    • 84874355365 scopus 로고    scopus 로고
    • SimpleScalar, http://www.simplescalar.com
    • SimpleScalar
  • 18
    • 46449112746 scopus 로고    scopus 로고
    • T. Pionteck, Dynamisch rekonfigurierbare Architekturen fur das digitale Basisband und für die Sicherungsschicht drahtloser Netzwerke, (in german), Dissertation, Technische Universität Darmstadt, 2004
    • T. Pionteck, "Dynamisch rekonfigurierbare Architekturen fur das digitale Basisband und für die Sicherungsschicht drahtloser Netzwerke", (in german), Dissertation, Technische Universität Darmstadt, 2004


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.