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Volumn 24, Issue 4, 2004, Pages 67-78

xDSPcore: A compiler-based configurable digital signal processor

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE DESCRIPTION LANGUAGES; DATA STORAGE EQUIPMENT; DIGITAL SIGNAL PROCESSING; EMBEDDED SYSTEMS; HIGH LEVEL LANGUAGES; OPTIMIZATION; REAL TIME SYSTEMS; SOFTWARE ENGINEERING;

EID: 4644342443     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2004.40     Document Type: Article
Times cited : (12)

References (12)
  • 5
    • 2442619275 scopus 로고    scopus 로고
    • DSPxPlore: Design space exploration methodology for an embedded DSP core
    • ACM Press
    • C. Panis, et al., "DSPxPlore: Design Space Exploration Methodology for an Embedded DSP Core," Proc. Symp. Applied Computing (SAC 04), ACM Press, 2004, pp. 876-883.
    • (2004) Proc. Symp. Applied Computing (SAC 04) , pp. 876-883
    • Panis, C.1
  • 8
    • 33745207900 scopus 로고    scopus 로고
    • Graph-coloring versus optimal register allocation for optimizing compilers
    • Lecture Notes in Computer Science, Springer Press
    • U. Hirnschrott, A. Krall, and B. Scholz, "Graph-Coloring Versus Optimal Register Allocation for Optimizing Compilers, Proc, Joint Modular Language Conf, (JMLC 03), Lecture Notes in Computer Science, Springer Press, 2003, pp. 202-213.
    • (2003) Proc, Joint Modular Language Conf, (JMLC 03) , pp. 202-213
    • Hirnschrott, U.1    Krall, A.2    Scholz, B.3
  • 9
    • 33745223764 scopus 로고    scopus 로고
    • Pointer alignment analysis for processors with SIMD instruction
    • Christian Doppler Laboratory Publications, Dec
    • Pryanishnikov, et al., "Pointer Alignment Analysis for Processors with SIMD Instruction," Proc. 5th Workshop on Media and Streaming Processors (MICRO 36), Christian Doppler Laboratory Publications, Dec. 2003, http://www.complang.tuwien.ac.at/cd/publications.html.
    • (2003) Proc. 5th Workshop on Media and Streaming Processors (MICRO 36)
    • Pryanishnikov1
  • 10
    • 0028768013 scopus 로고
    • Iterative modulo scheduling: An algorithm for software pipelining loops
    • ACM Press
    • B.R. Rau, "Iterative Modulo Scheduling: An Algorithm for Software Pipelining Loops," Proc. 27th Ann. Int'l Symp, Microarchitecture MICRO 27), ACM Press, 1994, pp. 63-74.
    • (1994) Proc. 27th Ann. Int'l Symp, Microarchitecture MICRO 27) , pp. 63-74
    • Rau, B.R.1
  • 11
    • 0026853681 scopus 로고
    • Low-power CMOS digital design
    • Apr
    • A.P. Chandrakasan, et al., "Low-Power CMOS Digital Design," IEEE Journal of Solid-State Circuits, vol. 27, no. 4, Apr. 1992, pp. 473-484.
    • (1992) IEEE Journal of Solid-State Circuits , vol.27 , Issue.4 , pp. 473-484
    • Chandrakasan, A.P.1
  • 12
    • 3042849412 scopus 로고    scopus 로고
    • VLIW operation refinement for reducing energy consumption
    • U. Hirnschrott and A. Krall, "VLIW Operation Refinement for Reducing Energy Consumption," Proc. Int'l Symp. System-On-Chip (SOC 03), 2003, http://www.complang.tuwien.ac.at/cd/soc2003.pdf.
    • (2003) Proc. Int'l Symp. System-On-Chip (SOC 03)
    • Hirnschrott, U.1    Krall, A.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.