A scaleable instruction buffer for a configurable DSP core

European Solid-State Circuits Conference

Volumn , Issue , 2003, Pages 49-52

  Panis, Christian ^a   Bramberger, Michael ^b   Grünbacher, Herbert ^a   Nurmi, Jari ^c  

^a Carinthian Tech Institute   (Austria)

^b INFINEON TECHNOLOGIES AUSTRIA AG   (Austria)

^c TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

CODE DENSITY; DSP PROCESSOR; MEMORY BANDWIDTHS; OUT-OF-ORDER EXECUTION; PROGRAM MEMORY; SOC APPLICATION; SYSTEM COMPLEXITY; VLIW(VERY LONG INSTRUCTION WORD);

DIGITAL SIGNAL PROCESSING; MICROPROCESSOR CHIPS; PARALLEL PROCESSING SYSTEMS;

VERY LONG INSTRUCTION WORD ARCHITECTURE;

EID: 4644339284     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2003.1257068     Document Type: Conference Paper

References (6)

1. P. Lapsley, J. Bier, A. Shoham and E. A. Lee, "DSP Processor Fundamentals, Architectures and Features", IEEE Press, New York 1997.
2. D. Sima, T. Fountain, P. Kacsuk, "Advanced Computer Architectures: A Design Space Approach", Addison Wesley Publishing Company, Harlow, 1997.
3. C. Panis, R. Leitner, H. Grunbacher, J. Nurmi "xLIW- a Scaleable Long Instruction Word", lSCAS 2003, Bangkok, Thailand, 2003.
4. C. Panis, G. Laure, W. Lazian, A. Krall, H. Grunbacher, J. Nurmi "DSPxPlore- Design Space Exploration for a Configurable DSP Core", GSPx 2003, Dallas, Texas, USA, 2003.
5. J. Handy, "The Cache Memory Book", Academic Press, 1998
6. O. Weiss, M. Gansen, T. G. Noll, "A flexible Datapath Generator for Physical Oriented Design", Proceedings of the ESSClRC 2001, Villach, 18.-20. September 2001, pp. 408-41 1