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Volumn , Issue , 2003, Pages 131-134

VLIW operation refinement for reducing energy consumption

Author keywords

[No Author keywords available]

Indexed keywords

BASIC BLOCKS; COMPILER OPTIMIZATIONS; DSP BENCHMARKS; DYNAMIC POWER DISSIPATION; ENERGY CONSUMPTION; FUNCTIONAL UNITS; GENETIC EVOLUTION; INSTRUCTION FETCH; LOW POWER; MOBILE COMPUTERS; OBJECTIVE FUNCTIONS; OPERATION REFINEMENT; OPTIMAL ALGORITHM; REDUCING ENERGY CONSUMPTION; SOFTWARE OPTIMIZATION; SWITCHING ACTIVITIES; VARIABLE LENGTH; VLIW ARCHITECTURES; VLIW PROCESSOR;

EID: 3042849412     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (5)

References (10)
  • 2
    • 0003147684 scopus 로고
    • Low power architecture design and compilation techniques for high-performance processors
    • IEEE, April
    • C.-L. Su, C.-Y. Tsui, and A. M. Despain, "Low power architecture design and compilation techniques for high-performance processors," in Proceedings of IEEE CompCon'94. IEEE, April 1994, pp. 489-498.
    • (1994) Proceedings of IEEE CompCon'94 , pp. 489-498
    • Su, C.-L.1    Tsui, C.-Y.2    Despain, A.M.3
  • 8
    • 33645425800 scopus 로고    scopus 로고
    • An operation rearrangement technique for power optimization in VLIW instruction fetch
    • ACM, March
    • D. Shin, J. Kim, and N. Chang, "An operation rearrangement technique for power optimization in VLIW instruction fetch," in Proceedings of Design, Automation and Test in Europe, Date'01. ACM, March 2001, pp. 809-817.
    • (2001) Proceedings of Design, Automation and Test in Europe, Date'01 , pp. 809-817
    • Shin, D.1    Kim, J.2    Chang, N.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.