Using internal redundant representations and limited bypass to support pipelined adders and register files

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn 2002-January, Issue , 2002, Pages 289-298

  Brown, M D ^a   Patt, Y N ^a  

^a The University of Texas at Austin   (United States)

Author keywords

Bandwidth; Clocks; Delay; Feeds; Frequency; Logic; Microprocessors; Out of order; Processor scheduling; Registers

Indexed keywords

BANDWIDTH; BINS; CLOCKS; COMPLEX NETWORKS; COMPUTER ARCHITECTURE; FEEDING; MICROPROCESSOR CHIPS; NETWORK ARCHITECTURE; SUPERCOMPUTERS;

DELAY; FREQUENCY; LOGIC; OUT OF ORDER; PROCESSOR SCHEDULING; REGISTERS;

ADDERS;

EID: 4644304391     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2002.995718     Document Type: Conference Paper

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