Rapid IP design of variable-length cached-FFT processor for OFDM-based communication systems

2006 IEEE Workshop on Signal Processing Systems Design and Implementation, SIPS

Volumn , Issue , 2006, Pages 62-65

  Lee, Yu Hung ^a   Yu, Tzu Hao ^a   Huang, Kuo Ken ^a   Wu, An Yeu ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMMUNICATION; COMMUNICATION SYSTEMS; CONCURRENT ENGINEERING; DATA STORAGE EQUIPMENT; ELECTRON BEAM LITHOGRAPHY; FOURIER TRANSFORMS; FREQUENCY ALLOCATION; FREQUENCY DIVISION MULTIPLEXING; INTEGRATED CIRCUITS; INTERNET PROTOCOLS; JOB ANALYSIS; LOCAL AREA NETWORKS; ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING; PRODUCT DEVELOPMENT; PROGRAMMABLE LOGIC CONTROLLERS; RAPID PROTOTYPING; SIGNAL PROCESSING; STANDARDS; TELECOMMUNICATION SYSTEMS; WIRELESS LOCAL AREA NETWORKS (WLAN);

CMOS TECHNOLOGIES; DESIGN FLOWS; DESIGN METHODOLOGIES; FAST FOURIER TRANSFORM (FFT); FFT PROCESSORS; FFT/IFFT; FLOATING POINT (FP); FULL CUSTOM INTELLECTUAL PROPERTY (IP) DESIGN; INVERSE FFT (IFFT); LOW-POWER CONSUMPTION; MEMORY STRUCTURES; OFDM SYSTEMS; OFDM-BASED COMMUNICATION SYSTEMS; PROTOTYPING; RE-DESIGNING; SIGNAL PROCESSING SYSTEMS; SIGNAL TO QUANTIZATION NOISE RATIO (SQNR); SIMULATION RESULTS; SOFT IP; SPEED REQUIREMENTS; SYSTEM ON CHIP (SOCS);

FAST FOURIER TRANSFORMS;

EID: 46249114183     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SIPS.2006.352556     Document Type: Conference Paper

References (9)

1. B. M. Baas, "A low-power, high-performance 1024-point FFT processor," IEEE Journal of Solid-State Circuits, vol. 34, no. 3, pp.380-387, 1999.
2. D. Elam and C. Lovescu, "A Block Floating Point Implementation for an N-Point FFT on the TMS320C55x DSP," Application report of Texas Instruments, Sep. 2003.
3. "A High Resolution FFT Processor", Application note of Zarlink Semiconductor, July 1993.
4. Y.-W. Lin, H.-Y. Liu, and C.-Y. Lee, "A Dynamic Scaling FFT Processor for DVB-T Applications," IEEE Journal of Solid-State Circuits, vol. 39, NO. 11, 2004.
5. J.-C. Kuo, C.-H. Wen, C.-H. Lin, and A.-Y. Wu, "VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-Based Communication Systems," EURASIP Journal on Appli, no. 13, pp. 1306-1316, Dec. 2003
6. Y. Zhao, A. T. Erdogan, and T. Arslan, "A Low-Power and Domain-Specific Reconfigurable FFT Fabric for System-on-Chip Applications," Parallel and Distributed Processing Symposium, 2005.
7. N. Miyamoto, L. Karnan, K. Maruo, K. Kotani, and T. Ohmi, "A Small-Area High-Performance 512-Point 2-Dimensional FFT Single-Chip Processor," Proceedings of the 29th European Solid-State Circuits, 2003.
8. L. Jia, Y. Gao, J. Isoaho, and H. Tenhunen, "A New VLSI-Oriented FFT Algorithm and Implementation," ASIC Conference 1998.
9. E. Bidet, D. Castelain, C. Joanblanq, and P. Senn, "A Fast Single-Chip Implementation of 8192 Complex Point FFT," IEEE Journal of Solid-State Circuits, vol. 30, no. 3, March 1995.