A small-area high performance 512-point 2-dimensional FFT single-chip processor

European Solid-State Circuits Conference

Volumn , Issue , 2003, Pages 603-606

  Miyamoto, Naoto ^a   Kaman, Leo ^a   Maruo, Kazuyuki ^b   Kotani, Koji ^a   Ohmi, Tadahiro ^a  

^a TOHOKU UNIVERSITY   (Japan)

^b ADVANTEST CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

FFT PROCESSORS; RADIX 2; RESOURCE SAVINGS; SINGLE CHIP PROCESSORS; SINGLE-CHIP; SMALL AREA;

MEMORY ARCHITECTURE;

FAST FOURIER TRANSFORMS;

EID: 84870169226     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2003.1257207     Document Type: Conference Paper

References (4)

1. W. Cooley et al., "An algorithm for the machine calculation of the Fourier Series, " Math. Comput., Vol. 9, pp. 292-301, 1965
2. Tom Chen et al., "COBRA: A 100-MOPS Single-Chip Programmable and Expandable FFT, " IEEE Trans, on VLSI Systems, Vol. 7, No. 2, pp. 174-182, 1999
3. Bevan M. Baas, "A Low-Power, High-Performance, 1024-Pint FFT Processor, " IEEE Journal of Solid-State Circuits, Vol. 34, No. 3, pp. 380-387, 1999
4. H. Miyanaga, et al., "A Real-Time 256 x 256 Point Two-Dimensional FFT Single-Chip Processor, " ICASSP, Vol. 2, pp. 1193-1196, 1991