Area and timing estimation for lookup table based FPGAs

Proceedings of European Design and Test Conference

Volumn , Issue , 1996, Pages 151-157

  Xu, Min ^a   Kurdahi, Fadi J ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN AIDS; ELECTRIC NETWORK SYNTHESIS; LOGIC DESIGN; TABLE LOOKUP;

AREA ESTIMATION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HIGH LEVEL SYNTHESIS; TIMING ESTIMATION;

LOGIC GATES;

EID: 0029771169     PISSN: 10661409     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)