Parallelizing DSP nested loops on reconfigurable architectures using data context switching

Proceedings - Design Automation Conference

Volumn , Issue , 2001, Pages 273-276

  Bondalapati, K ^a  

^a Chameleon Systems Inc   (United States)

Author keywords

Configurable computing; Loops; Mapping techniques

Indexed keywords

ANALOG TO DIGITAL CONVERSION; COMPUTATIONAL METHODS; COMPUTER ARCHITECTURE; DIGITAL SIGNAL PROCESSING; EMBEDDED SYSTEMS; MICROPROCESSOR CHIPS; SWITCHING SYSTEMS;

DATA CONTEXT SWITCHING (DSP); NESTED LOOPS;

PARALLEL PROCESSING SYSTEMS;

EID: 0034841274     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/378239.378483     Document Type: Conference Paper

References (5)

1. Mapping loops onto reconfigurable architectures
2. Loop pipelining optimization for reconfigurable architectures
3. Reconfigurable computing in wireless