C-based SoC design flow and EDA tools: An ASIC and system vendor perspective

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 19, Issue 12, 2000, Pages 1507-1522

  Wakabayashi, Kazutoshi ^a  

^a NEC CORPORATION   (Japan)

Author keywords

C based design; Dynamic reconfigurable computation; Floor plan; Hardware description language; Hardware software co simulation; High level synthesis; High level verification; Soc; Timing closure

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; C (PROGRAMMING LANGUAGE); COMPUTER AIDED DESIGN; COMPUTER HARDWARE; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; COMPUTER SOFTWARE; MICROPROCESSOR CHIPS;

DYNAMIC RECONFIGURABLE COMPUTATION; ELECTRONIC DESIGN AUTOMATION (EDA); SYSTEM-ON-A-CHIP (SOC) DESIGN;

INTEGRATED CIRCUIT LAYOUT;

EID: 0034428798     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.898829     Document Type: Article

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