Suppression of lateral charge redistribution using advanced impurity trap memory for improving high temperature retention

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2006, Pages

  Sunamura, Hiroshi ^a   Ikarashi, Taeko ^a   Morioka, Ayuka ^a   Kotsuji, Setsu ^a   Oshida, Makiko ^a   Ikarashi, Nobuyuki ^a   Fujieda, Shinji ^a   Watanabe, Hirohito ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DOPING (ADDITIVES); ELECTRON DEVICES; IMPURITIES; METALS; NONMETALS; SILICA;

CHARGE REDISTRIBUTION; CHARGE STORAGE; DEEP TRAPS; ELECTRON-CAPTURE EFFICIENCY; GATE OXIDES; HIGH TEMPERATURE; IMPURITY TRAPPING; METAL IMPURITIES; NON-VOLATILE MEMORIES; RETENTION IMPROVEMENT; SILICON DIOXIDES; TI ADDITIVES;

DATA STORAGE EQUIPMENT;

EID: 46049120282     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2006.346949     Document Type: Conference Paper

References (8)

1. M. Janai and B. Eitan, "The kinetics of degradation of data retention of post-cycled NROM non-volatile memory products", Proc. of IEEE Int. Rel. Phys. Symp. (IRPS), pp. 175-180, 2005.
2. L. Perniola, G. Iannaccone, B. De Salvo, G. Ghibaudo, G. Molas, C. Gerardi, and S. Deleonibus, "Experimental and theoretical analysis of scaling issues in dual-bit discrete trap non-volatile memories", IEDM Tech. Dig, pp.877-880 (35-3), 2005.
3. S. K. Samanta, P. K. Singh, W. J. Yoo, G. Samudra, Y.-C. Yeo, L. K. Bera, and N. Balasubramanian, "Enhancement of memory window in short channel non-volatile memory devices using double layer tungsten nanocrystals", IEDM Tech. Dig., pp. 177-180 (7-5), 2005.
4. 2 nanocrystal memory using spinodal phase separation of hafnium silicate", IEDM Tech. Dig., pp. 1080-1082, 2004.
5. B. Y. Choi, B.-G. Park, Y. K. Lee, S. K. Sung, T. Y. Kim, E. S. Cho, H. J. Cho, C. W. Oh, S. H. Kim, D. W. Kim, C.-H. Lee, and D. Park, "Highly scalable and reliable 2-bit/cell SONOS memory transistor beyond 50nm NVM technology using outer sidewall spacer scheme with damascence gate process", Symp. on VLSI Tech., pp.118-119, 2005.
6. H. Sunamura, K. Masuzaki, M. Terai, S. Kotsuji, T. Onizawa, A. Morioka, T. Ikarashi, N. Ikarashi, S. Fujieda, and H. Watanabe, "Ultra-uniform threshold voltage in SONOS-type non-volatile memory with novel charge trap layer formed by plasma nitridation", IEEE Non-Volatile Semiconductor Memory Workshop, pp.70-71, 2006.
7. 2", J. Appl. Phys., Vol. 48, pp.3425-3427, 1977.
8. L. Larcher, G. Verzellesi, P. Pavan, E. Lusky, I. Bloom, and B. Eitan, "Impact of programming charge distribution on threshold voltage and subthreshold slope of NROM memory cells", IEEE Trans. on Electron Devices, Vol. 49, pp. 1939-1946, 2002.